SM
S. R. Mansore
Ujjain Engineering College, Shri Govindram Seksaria Institute of Technology and Science
0000-0001-5091-8045
Employment
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Ujjain Engineering College Asso Professor1990 - Present
Education
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Shri Govindram Seksaria Institute of Technology and Science PhD2015 - 2019
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Shri Govindram Seksaria Institute of Technology and Science M.E.1998 - 2000
Projects & Funding
Projects & funding information is unavailable.
Publications (13)
- A Read-Decoupled Error-Tolerant 10T SRAM Cell in 32nm CMOS Technology Save
- A Highly Stable 10T SRAM Cell for Low Power Applications Save
- Design of a Single-Ended-Write Schmitt-Trigger Based 10T SRAM Cell Save
- A 32nm High Read Margin Single-Ended 9T SRAM Cell Save
- A Disturb-Free 9T SRAM Cell for Low Power Applications Save
- Single-ended 10T SRAM cell with improved stability Save
- Characterization of a single-ended Schmitt-trigger based 9T SRAM cell Save
- A 32 nm Read Disturb-free 11T SRAM Cell with Improved Write Ability Save
- A SINGLE-ENDED READ DISTURB-FREE PPN BASED 9T SRAM CELL Save
- A data-aware write-assist 10T SRAM cell with bit-interleaving capability Save