KADIYAM ANUSHA

About

Kadiyam Anusha has received her M.Tech. degree in VLSI System Design from St.Mary's Group of Institutions, Hyderabad (affiliated to JNTUH) in 2016. Currently, she is pursuing the Ph.D. degree in Electronics Engineering from the School of Electronics Engineering (SENSE), Department of Micro and Nano Electronics at VIT University Vellore, Tamil Nadu- 632014, India. Her research interest includes Thin-Film Transistors, Semiconductor Device Physics, and Modeling.

Employment

Employment history is unavailable.

Education

• Vellore Institute of Technology University Ph.D.
  2018 - Present
• St. Mary's Group of Institutions M.Tech VLSI System Design
  2014 - 2016

Projects & Funding

Projects & funding information is unavailable.

Publications (4)

• Numerical simulation and performance analysis of amorphous zinc oxynitride thin film transistor (a-ZnON TFT) for large area display applications
  Results in Engineering 2025 DOI: 10.1016/j.rineng.2025.105294
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• Comparative Study of DNTT-Based Low-Voltage BGBC, BGTC, TGBC and TGTC Configurations of OTFTs
  Organic Electronics - From Fundamentals to Applications [Working Title] 2024 DOI: 10.5772/intechopen.1006308
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• Enhancing device characteristics of pentacene-based organic transistors through graphene integration: A simulation study and performance analysis
  AIP Advances 2024 DOI: 10.1063/5.0218617
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• Review and analysis on numerical simulation and compact modeling of InGaZno thin-film transistor for display SENSOR applications
  Measurement: Sensors 2024 DOI: 10.1016/j.measen.2024.101391
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