Anindya Dhar

Employment

• Indian Institute of Technology Kharagpur Visiting Lecturer / Assistant Professor/ Associate Professor / Professor
  1996 - Present

Education

• Indian Institute of Technology Kharagpur Ph. D.
  1989 - 1993

Projects & Funding

Projects & funding information is unavailable.

Publications (10)

• Hybrid Adaptive Probabilistic Tabu Search Framework With Transformer-Model Surrogates and Attention Heatmaps for Accelerated Runtime and Combined Area–Power Efficient FSM State Encoding
  IEEE Access 2026 DOI: 10.1109/ACCESS.2026.3709337
  +Save
• Novel coprime MIMO configurations for DOA estimation with increased degrees of freedom
  Franklin Open 2025 DOI: 10.1016/j.fraope.2025.100374
  +Save
• A Fast Algorithm for Computation of General Integer-Order Hankel Transforms
  IEEE Signal Processing Letters 2025 DOI: 10.1109/LSP.2025.3592107
  +Save
• Comments on “Generalized Co-Prime MIMO Radar for DOA Estimation With Enhanced Degrees of Freedom”
  IEEE Sensors Journal 2025 DOI: 10.1109/JSEN.2025.3552712
  +Save
• Further Results on the Zero Redundancy Sparse Arrays for DOA Estimation
  IEEE Signal Processing Letters 2025 DOI: 10.1109/LSP.2025.3595069
  +Save
• ACBAM-Accuracy-Configurable Sign Inclusive Broken Array Booth Multiplier Design
  IEEE Transactions on Emerging Topics in Computing 2022 DOI: 10.1109/TETC.2021.3107509
  +Save
• FPGA fabric conscious architecture design and automation of speed-area efficient Margolus neighborhood based cellular automata with variegated scan path insertion
  Journal of Parallel and Distributed Computing 2022 DOI: 10.1016/j.jpdc.2022.04.020
  +Save
• A Novel $k$-times Extended Coprime Array for DOA Estimation With Increased Degrees of Freedom
  IEEE Signal Processing Letters 2022 DOI: 10.1109/LSP.2022.3182927
  +Save
• Novel Moving Coprime Array Configurations for Real-Valued Sources
  IEEE Signal Processing Letters 2022 DOI: 10.1109/LSP.2022.3151007
  +Save
• Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support
  Journal of Parallel and Distributed Computing 2021 DOI: 10.1016/j.jpdc.2021.01.005
  +Save