arka dutta

Employment

Employment history is unavailable.

Education

• Jadavpur University Ph.D.
  2014 - 2016

Projects & Funding

Projects & funding information is unavailable.

Publications (20)

• Influence of Channel length and High-K oxide Thickness on Subthreshold DC Performance of Graded Channel and Gate stack DG-MOSFETs
  2016
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• An Analytical BTBT Current Model of Symmetric/Asymmetric 4T Tunnel Double Gate FETs With Ambipolar Characteristic
  IEEE Transactions on Electron Devices 2016 DOI: 10.1109/TED.2016.2568998
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• Design and study of programmable ring oscillator using IDUDGMOSFET
  Solid-State Electronics 2016 DOI: 10.1016/j.sse.2015.11.009
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• Impact of temperature on linearity and harmonic distortion characteristics of underlapped FinFET
  Microelectronics Reliability 2016 DOI: 10.1016/j.microrel.2016.01.017
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• Influence of Underlap on Gate Stack DG-MOSFET for analytical study of Analog/RF performance
  Superlattices and Microstructures 2016 DOI: 10.1016/j.spmi.2016.04.013
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• Influence of channel length and high-K oxide thickness on subthreshold analog/RF performance of graded channel and gate stack DG-MOSFETs
  Microelectronics Reliability 2016 DOI: 10.1016/j.microrel.2016.03.001
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• Low-power amplitude modulator for wireless application using underlap double-gate metal-oxide-semiconductor field-effect transistor
  IET Circuits, Devices and Systems 2016 DOI: 10.1049/iet-cds.2015.0212
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• Physical Insights Into Electric Field Modulation in Dual-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math> </inline-formula> Spacer Asymmetric Underlap FinFET
  IEEE Transactions on Electron Devices 2016 DOI: 10.1109/TED.2016.2580625
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• Analysis of high-κ spacer asymmetric underlap DG-MOSFET for SOC application
  IEEE Transactions on Electron Devices 2015 DOI: 10.1109/TED.2015.2397699
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• Asymmetric underlap dual material gate DG-FET for low power analog/RF applications
  Journal of Low Power Electronics 2015 DOI: 10.1166/jolpe.2015.1415
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