Viveka Konandur Rajanna

About

Dr. Viveka Konandur Rajanna is an Assistant Professor in the Department of Electronic Systems Engineering (DESE) at Indian Institute of Science (IISc), Bangalore. He received his M.Tech. and Ph.D. degrees from IISc in 2007 and 2016 respectively. He worked as research fellow at the National University of Singapore (NUS), before joining the institute in 2022. He worked with Analog Devices Inc, Bangalore, between 2007 to 2010, developing Blackfin DSPs. His research interests include ultra-low power VLSI circuits, in-memory computing, memory design, low-power human sensor interface and secure on-chip computing.

Employment

• Indian Institute of Science Bangalore Assistant Professor
  2022 - Present
• Analog Devices Inc Design Engineer
  2007 - 2010
• National University of Singapore Research Fellow
• Berkeley Education Alliance for Research in Singapore Limited Postdoctoral Research Fellow

Education

• Indian Institute of Science PhD
  2010 - Present
• Indian Institute of Science M. Tech.
  2005 - 2007

Projects & Funding

Projects & funding information is unavailable.

Publications (12)

• SRAM Static Entropy Extraction From Every Single Transistor in Unmodified Bitcell and Data Fingerprinting for Provenance Assurance
  IEEE Journal of Solid-State Circuits 2026 DOI: 10.1109/JSSC.2025.3608858
  +Save
• In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security
  IEEE Journal of Solid-State Circuits 2022 DOI: 10.1109/jssc.2021.3125255
  +Save
• On-Chip Links With Energy-Quality Tradeoff in Error-Resilient and Machine Learning Applications
  IEEE Journal of Solid-State Circuits 2021 DOI: 10.1109/jssc.2021.3095343
  +Save
• SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm2 and 749-1,459 TOPS/W in 28nm
  ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) 2021 DOI: 10.1109/esscirc53450.2021.9567830
  +Save
• Fully-Digital Self-Calibrating Decoder with Sub-µW, 1.6fJ/convstep and 0.0075mm2 per Receptor for Scaling to Human-Like Tactile Sensing Density
  2021 Symposium on VLSI Circuits 2021 DOI: 10.23919/vlsicircuits52068.2021.9492329
  +Save
• 36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security
  2021 IEEE International Solid- State Circuits Conference (ISSCC) 2021 DOI: 10.1109/isscc42613.2021.9366019
  +Save
• Low-Swing Links with Dynamic Energy-Quality Trade-off for Error-Resilient Applications
  2019 IEEE Custom Integrated Circuits Conference (CICC) 2019 DOI: 10.1109/cicc.2019.8780323
  +Save
• A Variation-Tolerant Replica-Based Reference-Generation Technique for Single-Ended Sensing in Wide Voltage-Range SRAMs
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2016 DOI: 10.1109/tvlsi.2015.2469596
  +Save
• Energy Efficient Memory Decoder Design for Ultra-low Voltage Systems
  2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems 2014 DOI: 10.1109/vlsid.2014.32
  +Save
• Digitally controlled variation tolerant timing generation technique for SRAM sense amplifiers
  Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) 2013 DOI: 10.1109/asqed.2013.6643593
  +Save