ROSE GEORGE KUNTHARA

About

Currently I am working as a Senior Project Associate at Department of Electronics, CUSAT. Previously, I was a Research Scholar at Division of Electronics, School of Engineering CUSAT. My research interests include Computer architecture, Network on Chip and Multicore architectures

Employment

• Cochin University of Science and Technology Senior Project Associate
  2023 - Present
• SCHOOL OF ENGINEERING, CUSAT RESEARCH SCHOLAR
  2014 - Present
• ST. JOSEPHS COLLEGE OF ENGINEERING AND TECHNOLOGY ASSISTANT PROFESSOR
  2011 - 2013

Education

• BITS PILANI M.E. EMBEDDED SYSTEMS
  2009 - 2011
• SCHOOL OF ENGINEERING, CUSAT B-TECH
  2005 - 2009

Projects & Funding

Projects & funding information is unavailable.

Publications (14)

• Subnetwork Based Traffic Aware Rerouting for CMesh Bufferless Network-on-Chip
  Journal of Circuits, Systems and Computers 2024 1 citation DOI: 10.1142/S0218126624502074
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• Modelling and Impact Analysis of Antipode Attack in Bufferless On-Chip Networks
  SN Computer Science 2023 1 citation DOI: 10.1007/s42979-022-01622-y
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• Modelling and Impact Analysis of Push Back Attack in 3D Bufferless Network on Chip
  Proceedings - 2023 16th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2023 2023 0 citations DOI: 10.1109/MCSoC60832.2023.00070
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• DAReS: Deflection Aware Rerouting between Subnetworks in Bufferless On-Chip Networks
  Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 2022 3 citations DOI: 10.1145/3526241.3530332
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• Impact Analysis of Communication Overhead in NoC based DNN Hardware Accelerators
  INDICON 2022 - 2022 IEEE 19th India Council International Conference 2022 1 citation DOI: 10.1109/INDICON56171.2022.10039775
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• RIBiT: Reduced Intra-flit Bit Transitions for Bufferless NoC
  IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2022 7 citations DOI: 10.1109/VLSI-SoC54400.2022.9939590
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• Traffic aware routing in 3D NoC using interleaved asymmetric edge routers
  Nano Communication Networks 2021 13 citations DOI: 10.1016/j.nancom.2020.100334
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• Dual Stage Encoding Technique to Minimize Cross Coupling across NoC Links
  2021 25th International Symposium on VLSI Design and Test, VDAT 2021 2021 1 citation DOI: 10.1109/VDAT53777.2021.9601003
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• Interleaved Edge Routing in Buffered 3D Mesh CMesh NoC
  2021 8th International Conference on Smart Computing and Communications: Artificial Intelligence, AI Driven Applications for a Smart World, ICSCC 2021 2021 3 citations DOI: 10.1109/ICSCC51209.2021.9528183
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• 2L-2D Routing for Buffered Mesh Network-on-Chip
  2019 3 citations DOI: 10.1007/978-981-32-9767-8_27
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