Sushant Mittal

Employment

• Indian Institute of Technology BHU Varanasi Assistant Professor
  2020 - Present
• Applied Materials India Private Limited Senior Technical Manager
  2017 - 2020
• Micron Technology Inc Device Engineer
  2016 - 2017
• NVIDIA Corp ASIC Design Engineer
  2008 - 2010

Education

• Indian Institute of Technology Bombay Ph.D.
  2010 - 2017
• Indian Institute of Technolog B.Tech.
  2004 - 2008

Projects & Funding

Projects & funding information is unavailable.

Publications (22)

• Via Size Optimization for Optimum Circuit Performance at 3 nm node
  2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2020 DOI: 10.23919/sispad49475.2020.9241685
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• Impact of MOL/BEOL Air-Spacer on Parasitic Capacitance and Circuit Performance at 3 nm Node
  2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2019 DOI: 10.1109/sispad.2019.8870410
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• Highly-Doped Through-Contact Silicon Epi Design at 3 nm node
  2019 Device Research Conference (DRC) 2019 DOI: 10.1109/drc46940.2019.9046479
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• An accurate expression to estimate the metal gate granularity induced threshold voltage variability in NWFETs
  Solid-State Electronics 2019 DOI: 10.1016/j.sse.2018.12.003
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• The First Compact Model to Determine <inline-formula> <tex-math notation="LaTeX">$V_{T}$ </tex-math> </inline-formula> Distribution for DG-FinFET Due to LER
  IEEE Transactions on Electron Devices 2018 DOI: 10.1109/ted.2018.2870282
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• Scaling NC-FinFET to Sub-3 nm Nodes
  2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) 2018 DOI: 10.1109/s3s.2018.8640184
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• Analytical modeling of metal gate granularity based threshold voltage variability in NWFET
  Solid-State Electronics 2018 DOI: 10.1016/j.sse.2018.05.007
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• Selective Fin Trimming after Dummy Gate Removal as the Local Fin Width Scaling Approach for N5 and Beyond
  2018 IEEE International Electron Devices Meeting (IEDM) 2018 DOI: 10.1109/iedm.2018.8614487
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• Analytical Estimation of Threshold Voltage Variability by Metal Gate Granularity in FinFET
  IEEE Transactions on Electron Devices 2017 DOI: 10.1109/ted.2017.2712763
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• Analytical Model to Estimate FinFET’s ${\text I}_{\text {ON}}$ , ${\text I}_{\text{OFF}}$ , SS, and ${\rm V}_{T}$ Distribution Due to FER
  IEEE Transactions on Electron Devices 2017 DOI: 10.1109/ted.2017.2709619
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