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Publications (8)
- Improving robustness and variability tolerance in SRAM-based in-memory computing using body bias Save
- Aging-Aware Timing Models for Reliability Enhancement of Inverter-Transmission Gate-Based Circuits Save
- Efficient total ionizing dose-aware standard cell characterization methodology for path-level timing performance in nanoscale digital circuit applications Save
- DAAS: Differential Aging-Aware STA for Precise Timing Closure With Reduced Design Margin Save
- A Methodology for Datapath Energy Prediction and Optimization in Near Threshold Voltage Regime Save
- Robust and Reliable Energy-Efficient Level Shifter Save
- Switching Activity Factor-Based ECSM Characterization (SAFE): A Novel Technique for Aging-Aware Static Timing Analysis Save
- Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort Save