Dr. Dharmendra Singh Yadav

Employment

• National Institute of Technology Kurukshetra Assistant Professor (Grade-I)
• National Institute of Technology Hamirpur Assistant Professor

Education

Education history is unavailable.

Projects & Funding

Projects & funding information is unavailable.

Publications (23)

• A novel approach to improve the performance of charge plasma tunnel field-effect transistor
  IEEE Transactions on Electron Devices 2018 38 citations DOI: 10.1109/TED.2017.2766262
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• Temperature based performance analysis of doping-less tunnel field effect transistor
  IEEE International Conference on Information, Communication, Instrumentation and Control, ICICIC 2017 2018 15 citations DOI: 10.1109/ICOMICON.2017.8279131
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• Study of metal strip insertion and its optimization in doping less TFET
  Superlattices and Microstructures 2018 16 citations DOI: 10.1016/j.spmi.2018.06.046
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• Performance analysis of gate all around GaAsP/AlGaSb CP-TFET
  Superlattices and Microstructures 2018 21 citations DOI: 10.1016/j.spmi.2018.03.049
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• High Frequency Analysis of GaAsP /InSb Hetero-Junction Double Gate Tunnel Field Effect Transistor
  2018 3rd International Conference for Convergence in Technology, I2CT 2018 2018 3 citations DOI: 10.1109/I2CT.2018.8529594
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• Hetero-material CPTFET with high-frequency and linearity analysis for ultra-low power applications
  Micro and Nano Letters 2018 14 citations DOI: 10.1049/mnl.2018.5075
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• Effective design technique for improvement of electrostatics behaviour of dopingless TFET: Proposal, investigation and optimisation
  Micro and Nano Letters 2018 9 citations DOI: 10.1049/mnl.2018.5129
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• Controlling ambipolar current of dopingless tunnel field-effect transistor
  Applied Physics A: Materials Science and Processing 2018 17 citations DOI: 10.1007/s00339-018-2237-6
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• Controlling ambipolar behavior and improving radio frequency performance of hetero junction double gate TFET by dual work-function, hetero gate dielectric, gate underlap: Assessment and optimization
  IEEE International Conference on Information, Communication, Instrumentation and Control, ICICIC 2017 2018 7 citations DOI: 10.1109/ICOMICON.2017.8279132
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• A systematic investigation of the integrated effects of gate underlapping, dual work functionality and hetero gate dielectric for improved performance of CP TFETs
  Journal of Computational Electronics 2018 7 citations DOI: 10.1007/s10825-017-1045-0
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