Sourav Dutta

About

I am currently a postdoctoral research associate in the NDCL lab working with Dr. Suman Datta in Electrical Engineering at University of Notre Dame. I received my B.Tech in Electrical Engineering from Jadavpur University, Kolkata, India, in 2012 and my Ph.D. in Electrical and Computer Engineering from Georgia Institute of Technology, Atlanta, USA where I worked with Dr. Azad Naeemi.

My current research focuses on emerging device architecture exploration and implementation to enable brain-inspired computing. My work involves experimental characterization, modeling and simulation of ferroelectric and phase-change materials for enabling neural network and coupled oscillator based neuromorphic hardware. Previously, I have worked on modeling and simulation of spintronic devices and interconnects for Beyond-CMOS application during my PhD. From May to July 2016, I was a visiting researcher at IMEC, Belgium where I was involved in modeling and simulation of nanoscale plasmonic logic gates, magneto-plasmonics and spin-plasmonics for boolean and non-boolean computation for Beyond-CMOS application.

I am the recipient of the 2018 Sigma Xi Best Ph.D. Thesis Award at Georgia Tech and 2009 Kishore Vaigyanik Protsahan Yojana (Young Scientist Encouragement Program) Fellowship in India.

Employment

• University of Notre Dame Postdoctoral Research Associate
  2018 - Present
• Georgia Institute of Technology Graduate Research Assistant
  2012 - 2017

Education

• Georgia Institute of Technology

Projects & Funding

Projects & funding information is unavailable.

Publications (21)

• FIMA: A Scalable Ferroelectric Compute-in-Memory Annealer for Accelerating Boolean Satisfiability
  IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 2025 1 citation DOI: 10.1109/JXCDC.2025.3603942
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• An Optimized SPICE-Compatible Positive Feedback Model for Ferroelectric Devices: Design, Calibration, and Dynamic Simulations
  IEEE Transactions on Electron Devices 2025 1 citation DOI: 10.1109/TED.2025.3574704
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• A Compute-in-Memory Hardware Accelerator Design With Back-End-of-Line (BEOL) Transistor Based Reconfigurable Interconnect
  IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2022 19 citations DOI: 10.1109/JETCAS.2022.3177577
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• Neural sampling machine with stochastic synapse allows brain-like learning and inference
  Nature Communications 2022 67 citations DOI: 10.1038/s41467-022-30305-8
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• BEOL-Compatible Superlattice FEFET Analog Synapse With Improved Linearity and Symmetry of Weight Update
  IEEE Transactions on Electron Devices 2022 69 citations DOI: 10.1109/TED.2022.3142239
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• Logic Compatible High-Performance Ferroelectric Transistor Memory
  IEEE Electron Device Letters 2022 91 citations DOI: 10.1109/LED.2022.3148669
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• An Ising Hamiltonian solver based on coupled stochastic phase-transition nano-oscillators
  Nature Electronics 2021 171 citations DOI: 10.1038/s41928-021-00616-7
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• Experimental Demonstration of Gate-Level Logic Camouflaging and Run-Time Reconfigurability Using Ferroelectric FET for Hardware Security
  IEEE Transactions on Electron Devices 2021 23 citations DOI: 10.1109/TED.2020.3045380
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• Understanding the Continuous-Time Dynamics of Phase-Transition Nano-Oscillator-Based Ising Hamiltonian Solver
  IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 2020 18 citations DOI: 10.1109/JXCDC.2020.3045074
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• Simulation of the Magnetization Dynamics of a Single-Domain BiFeO₃ Nanoisland
  IEEE Transactions on Magnetics 2020 15 citations DOI: 10.1109/TMAG.2020.3011932
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