SURAJ KUMAR SAW

Employment

• IIIT SURAT FACULTY
  2020 - Present

Education

• National Institute of Technology Arunachal Pradesh Ph.D
  2016 - 2020

Projects & Funding

Projects & funding information is unavailable.

Publications (21)

• PVT Aware Design of a Dead-zone Free High Speed Phase Frequency Detector in 90nm CMOS
  Recent Advances in Electrical & Electronic Engineering 2020 DOI: 10.2174/2352096512666190314111752
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• A design approach of higher oscillation VCO made of CS amplifier with varying active load
  Microsystem Technologies 2019 DOI: 10.1007/s00542-019-04500-5
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• A hybrid design approach of PVT tolerant, power efficient ring VCO
  Ain Shams Engineering Journal 2019 DOI: 10.1016/j.asej.2019.10.009
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• A power efficient PFD-CP architecture for high speed clock and data recovery application
  Microsystem Technologies 2019 DOI: 10.1007/s00542-019-04458-4
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• Design of differential amplifier using current mirror load in 90 nm CMOS technology
  Advances in Intelligent Systems and Computing 2019 DOI: 10.1007/978-981-13-3329-3_39
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• Passive element free variation aware decision circuit for 40 Gb/s CDR application
  Microsystem Technologies 2019 DOI: 10.1007/s00542-019-04683-x
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• Variation aware design of 50-Gbit/s, 5.027-fJ/bit serializer using latency combined mux-dual latch for inter-chip communication
  IEEE Transactions on Circuits and Systems I: Regular Papers 2019 DOI: 10.1109/TCSI.2018.2877571
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• A power efficient charge pump circuit configuration for fast locking PLL application
  Microsystem Technologies 2018 DOI: 10.1007/s00542-018-4037-5
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• An energy efficient PVT aware novel CML-TG based Mux-Latch circuit Serializes high rate data
  Microsystem Technologies 2018 DOI: 10.1007/s00542-018-4093-x
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• Design of high frequency D flip flop circuit for phase detector application
  IEEE Region 10 Annual International Conference, Proceedings/TENCON 2017 DOI: 10.1109/TENCON.2017.8227867
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