Suman Das

About

I am pursuing my Ph.D in Engineering and Technology from Institute of Radio physics and Electronics, University of Calcutta, India. I did M.Tech in VLSI & Microelectronics from Techno India under West Bengal University of technology in 2014. I received my B.Tech in Electronics and Communication Engineering from St. Thomas College of Engineering and Technology under west Bengal University of technology in 2011. Presently, I am working as an Assistant Professor in the Department of Electronics and communication engineering, Sikkim Manipal Institute of Technology, Sikkim Manipal University, India. I have received the University Gold Medal from West Bengal University of Technology, West Bengal, India in 2015. I have also received the certificate of merit and Medal from Techno India for securing 1st position in M.Tech examination in 2013 and 2014 consecutively. I have 6 Yrs. and 06 months teaching experiences.

Employment

• Sikkim Manipal Institute of Technology - Majitar Assistant Professor
  2014 - Present

Education

Education history is unavailable.

Projects & Funding

Projects & funding information is unavailable.

Publications (11)

• Influence of High Temperature on Digital and Analog Performance of Unique U-shaped Channel TFET for 0.8 V and sub-0.4 V Operation
  Arabian Journal for Science and Engineering 2026 DOI: 10.1007/s13369-025-10877-5
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• An extensive review of THz communication in 6G: Facilitating technologies with edge computing and native AI
  Franklin Open 2025 DOI: 10.1016/j.fraope.2025.100434
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• Layer-dependent performance analysis of black phosphorus Double-Gate TFETs for optimized nanoelectronic applications
  Micro and Nanostructures 2025 DOI: 10.1016/j.micrna.2025.208354
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• Investigation of Double-Gate MoS2 TFETs in Design Space: Impact of Channel Thickness on Analog, RF, Linearity, and Harmonic Distortion
  Journal of Electronic Materials 2025 DOI: 10.1007/s11664-025-12349-w
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• Effect of Channel Epilayer Thickness on Low Power Analog Operation of Asymmetric U-Shaped pTFET
  2024 DOI: 10.1007/978-981-97-1571-8_6
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• Asymmetric-Elevated-Source-Drain TFET: A Fairly Scalable and Reliable Device Architecture for Sub-400-mV Low-Stand-by-Power Digital Applications
  IETE Technical Review 2020
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• Minimization of Drain-End Leakage of a U-Shaped Gated Tunnel FET for Low Standby Power (LSTP) Application
  Nanoelectronics, Circuits and Communication Systems 2020
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• nTunnel FET (nTFET) Reliability Study Against Positive Bias Temperature Instability (PBTI) for Different Device Architectures
  Proceedings of the Fourth International Conference on Microelectronics, Computing and Communication Systems 2020
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• VLSI Implementation of Booth’s Multiplier Using Different Adders
  Advances in Communication, Devices and Networking 2018
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• A MATLAB-Based Simulator for Amorphous Silicon and Polycrystalline Silicon Thin Film Transistor
  Advances in Electronics, Communication and Computing 2017
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