K VANLALAWMPUIA

Employment

• national institute of technology Mizoram

Education

Education history is unavailable.

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Projects & funding information is unavailable.

Publications (13)

• Analysis of Hetero-Stacked Source TFET and Heterostructure Vertical TFET as Dielectrically Modulated Label-Free Biosensors
  IEEE Sensors Journal 2022 DOI: 10.1109/JSEN.2021.3128473
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• Interfacial charge analysis and temperature sensitivity of germanium source vertical tunnel FET with delta-doped layer
  Microelectronics Reliability 2022 DOI: 10.1016/j.microrel.2022.114512
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• Lateral Straggle Parameter and Its Impact on Hetero-Stacked Source Tunnel FET
  Lecture Notes in Electrical Engineering 2022 DOI: 10.1007/978-981-16-9124-9_8
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• Analysis of Temperature Dependent Effects on DC, Analog/RF and Linearity Parameters for a Delta Doped Heterojunction Vertical tunnel FET
  Silicon 2021 DOI: 10.1007/s12633-021-01504-7
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• Investigation of interface trap charges and temperature variation in heterostacked-TFET
  Indian Journal of Physics 2021 DOI: 10.1007/s12648-020-01834-z
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• Optimization of a Hetero-Structure Vertical Tunnel FET for Enhanced Electrical Performance and Effects of Temperature Variation on RF/Linearity Parameters
  Silicon 2021 DOI: 10.1007/s12633-020-00411-7
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• Study on induced work-function variation of titanium metal gate on various electrical parameters for delta-doped layer germanium source vertical tunnel FET
  Journal of Computational Electronics 2021 DOI: 10.1007/s10825-021-01686-8
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• Linearity Performance Analysis Due to Lateral Straggle Variation in Hetero-Stacked TFET
  Silicon 2020 DOI: 10.1007/s12633-019-00189-3
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• Study of effect of oxide thickness variation on electrical parameters and high frequency characteristics induced by work-function variation for delta-doped germanium-source vertical TFET
  Semiconductor Science and Technology 2020 DOI: 10.1088/1361-6641/aba823
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• Deep insight into DC, RF/analog, and digital inverter performance due to variation in straggle parameter for gate modulated TFET
  Materials Science in Semiconductor Processing 2019 DOI: 10.1016/j.mssp.2018.11.011
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