Sreejeesh SG

Employment

• National Institute of Electronics and Information Technology - Calicut Senior Technical Officer
  2007 - Present
• NTT Sentan Gijutsu Sogo Kenkyujo
  2003 - 2003

Education

• Vellore Institute of Technology University Master of Technology
  2018 - 2020

Projects & Funding

Projects & funding information is unavailable.

Publications (16)

• Design of a Digital Receive Beamformer ASIC Based Ultrasound Imaging System Prototype
  Journal of Circuits, Systems and Computers 2025 DOI: 10.1142/S0218126625500641
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• An FPGA Implementation of Gigabit Ethernet Data Transfer Scheme for Ultrasound Imaging
  International Conference on Communication, Electronics and Digital Technology 2023
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• An FPGA-Accelerated Parallel Digital Beamforming Core for Medical Ultrasound Sector Imaging
  IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control 2022 DOI: 10.1109/TUFFC.2021.3126578
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• Design of a 128‐channel transceiver hardware for medical ultrasound imaging systems
  IET Circuits, Devices & Systems 2021 DOI: 10.1049/cds2.12087
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• An Efficient Parallel Architecture for Sub Band Processor in Broad Band MVDR Beamformer for Medical Ultrasound Applications
  International Journal of Emerging Technology and Advanced Engineering 2021 DOI: 10.46338/ijetae0621_04
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• Superior Implementation of Accelerated QR Decomposition for Ultrasound Imaging
  IEEE Access 2020 DOI: 10.1109/ACCESS.2020.3017558
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• Beamforming algorithm architectures for medical ultrasound
  International Journal of Innovative Technology and Exploring Engineering 2019 DOI: 10.35940/ijitee.L2556.1081219
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• Design and physical implementation of array signal processor ASIC for sector imaging systems
  Proceedings - 32nd International Conference on VLSI Design, VLSID 2019 - Held concurrently with 18th International Conference on Embedded Systems, ES 2019 2019 DOI: 10.1109/VLSID.2019.00095
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• Implementation of I2C master bus controller on FPGA
  International Conference on Communication and Signal Processing, ICCSP 2013 - Proceedings 2013 DOI: 10.1109/iccsp.2013.6577229
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• Design of Configurable IP core for Error Detection and Correction
  International Conference on Control Communication & Computer Technology 2012
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