nalini bodasingi

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Publications (9)

• Modified priority encoder based hardware efficient N-bit comparator
  International Journal of Electronics Letters 2023 DOI: 10.1080/21681724.2022.2117848
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• A Low Error, Hardware Efficient Logarithmic Multiplier
  Circuits, Systems, and Signal Processing 2022 DOI: 10.1007/s00034-021-01793-8
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• Automatic diagnosis of pneumonia using backward elimination method based SVM and its hardware implementation
  International Journal of Imaging Systems and Technology 2022 DOI: 10.1002/ima.22694
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• Hardware efficient circuit for low error logarithmic converter
  Journal of Computational Methods in Sciences and Engineering 2022 DOI: 10.3233/JCM-215778
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• Hardware-efficient approximate logarithmic division with improved accuracy
  International Journal of Circuit Theory and Applications 2021 DOI: 10.1002/cta.2900
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• FPGA Implementation of USB 3.1 Physical Coding Layer
  Proceedings of the 2nd International Conference on Computing Methodologies and Communication, ICCMC 2018 2018 DOI: 10.1109/ICCMC.2018.8487803
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• FPGA implementation of BASK-BFSK-BPSK-DPSK digital modulators using system generator
  Proceedings of IEEE International Conference on Circuit, Power and Computing Technologies, ICCPCT 2017 2017 DOI: 10.1109/ICCPCT.2017.8074203
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• Development of a VLSI based Real-Time system for carcinoma detection and identification
  Lecture Notes in Electrical Engineering 2016 DOI: 10.1007/978-81-322-2728-1_5
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• VLSI implementation of modified daubechies architecture for brain disease detection and identification
  2014 International Conference on Electronics and Communication Systems, ICECS 2014 2014 DOI: 10.1109/ECS.2014.6892697
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