SR
Shivendra Rathaur
Indian Institute of Technology Kanpur, Indian Institute of Technology Mandi
0000-0001-6847-8092
Employment
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Indian Institute of Technology Kanpur Project Engineer2019 - 2019
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Indian Institute of Technology Mandi Project Associate2018 - 2018
Education
Education history is unavailable.
Projects & Funding
Projects & funding information is unavailable.
Publications (10)
- Improvement of the Enhancement-Mode GaN MIS-HEMTs by Fluorine Doping in the Dielectric Gate Stack Save
- Impact of temperature on threshold voltage instability under negative bias in ferroelectric charge trap (FEG) GaN-HEMT Save
- Performance and Threshold Voltage Reliability of Quaternary InAlGaN/GaN MIS-HEMT on Si for Power Device Applications Save
- Investigation on Positive Bias-Induced Threshold Voltage Instability in GaN-on-Si D-mode Power MIS-HEMTs Save
- Investigation on Traps Dynamics & Negative Bias Stress in D-Mode GaN-on-Si Power MIS HEMTs Under High-Temperature Save
- Low contact resistance and high breakdown voltage of AlGaN/GaN HEMT grown on silicon using both AlN/GaN superlattice and Al0.07Ga0.93N back barrier layer Save
- Reliability assessment of high-power GaN-HEMT devices with different buffers under influence of gate bias and high-temperature tests Save
- High-Temperature TDDB Investigation on High Performance-Centered Hybrid HZO/HfON/Al2O3, Ferro-Electric Charge-Trap (FEG) GaN-HEMT Save
- Time-dependent Multiple Gate Voltage Reliability of Hybrid Ferroelectric Charge Trap Gate Stack (FEG) GaN HEMT for Power Device Applications Save
- Metal (Pt)/ferroelectric (SrBi2Ta2O9)/insulator (La2O3)/semiconductor (Si), MFIS structures for nonvolatile memory applications Save