Rashi Chaudhary

Employment

Employment history is unavailable.

Education

Education history is unavailable.

Projects & Funding

Projects & funding information is unavailable.

Publications (17)

• Analysis of thermal stability in underlap and overlap DMG FinFETs including self-heating effects
  Microelectronics Journal 2024 DOI: 10.1016/j.mejo.2024.106152
  +Save
• Quality factor and digital inverter performance in gate underlap and overlap DMG FinFETs
  Materials Science and Engineering: B 2024 DOI: 10.1016/j.mseb.2023.116991
  +Save
• Physical insights of interface traps and self-heating effect on electrical response of DMG FinFETs in overlap and underlap configurations: analog/RF perspective
  Physica Scripta 2024 DOI: 10.1088/1402-4896/ad16b0
  +Save
• Performances of gate stacked heterojunction SELBOX and SOI tunnel FETs including interface trap charges: A simulation study
  Materials Science and Engineering: B 2024 DOI: 10.1016/j.mseb.2023.117115
  +Save
• Performance Analysis of FinFET based Operational Amplifier at 20 nm gate Length
  2024 IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation, IATMSI 2024 2024 DOI: 10.1109/IATMSI60426.2024.10503453
  +Save
• Investigation on electrical parameters between single and double material gate nanoribbon FETs including trap distributions
  Materials Science and Engineering: B 2024 DOI: 10.1016/j.mseb.2024.117326
  +Save
• Impact of self-heating on geometric variations in nano-ribbon FET: Analog/RF perspective
  Micro and Nanostructures 2024 DOI: 10.1016/j.micrna.2024.207908
  +Save
• Energy Efficient Vedic Multiplier
  2024 IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation, IATMSI 2024 2024 DOI: 10.1109/IATMSI60426.2024.10502729
  +Save
• Elimination of the impact of trap charges through heterodielectric BOX in nanoribbon FET
  Nanoelectronic Devices and Applications 2024 DOI: 10.2174/9789815238242124010014
  +Save
• Analysis on the impact of interface Trap distributions on SOI DMG FinFETs: Overlap/underlap configurations
  Micro and Nanostructures 2024 DOI: 10.1016/j.micrna.2023.207725
  +Save