Nithin Kumar

Employment

• National Institute of Technology Goa Associate Professor

Education

Education history is unavailable.

Projects & Funding

Projects & funding information is unavailable.

Publications (82)

• MFDFA-Enhanced GAN: A Hardware-Optimized Architecture for Efficient Synthetic Image Generation
  IEEE Access 2026 0 citations DOI: 10.1109/ACCESS.2026.3677066
  +Save
• A Power-Efficient High-Speed D-Latch Architecture for Enhanced PDP Performance
  IEEE Access 2026 0 citations DOI: 10.1109/ACCESS.2026.3683583
  +Save
• Evolutionary-Enhanced GAN With Wavelet-Based Discrimination: A Hardware-Accelerated Architecture for Efficient Synthetic Image Generation
  IEEE Access 2025 0 citations DOI: 10.1109/ACCESS.2025.3642041
  +Save
• Generating Synthetic Data Using 2D Multifractal Detrended Fluctuation Analysis Generative Adversarial Networks
  IEEE Access 2025 0 citations DOI: 10.1109/ACCESS.2025.3603332
  +Save
• An exponential variation based PSO for analog circuit sizing in constrained environment
  AEU - International Journal of Electronics and Communications 2024 4 citations DOI: 10.1016/j.aeue.2024.155531
  +Save
• A 1.2 V Single Event Multinode Upset Tolerant RHSC 12T Memory Cell in 65-nm CMOS
  IEEE Transactions on Electron Devices 2024 14 citations DOI: 10.1109/TED.2023.3343316
  +Save
• An Error Bound Particle Swarm Optimization for Analog Circuit Sizing
  IEEE Access 2024 7 citations DOI: 10.1109/ACCESS.2024.3385491
  +Save
• N-Parallel Paths-Based D-Latch for High-Speed Applications
  IEEE Access 2024 3 citations DOI: 10.1109/ACCESS.2024.3491577
  +Save
• Partition Bound Random Number-Based Particle Swarm Optimization for Analog Circuit Sizing
  IEEE Access 2023 6 citations DOI: 10.1109/ACCESS.2023.3329698
  +Save
• A 1-V, 5-bit, 180-µW, differential pulse position modulation ADC in 65-nm CMOS process
  Proceedings - IEEE International Symposium on Circuits and Systems 2021 3 citations DOI: 10.1109/ISCAS51556.2021.9401108
  +Save