Vishram S Pandit

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Publications (18)

• Power delivery noise and its impact on jitter and system margin for multi-Gb/s high-speed serial interfaces
  DesignCon 2015 2015
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• PI, SI and Circuit co-design of LPDDR4 and LPDDR3
  DesignCon 2015 2015
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• Analysis and correlations of supply noise and jitter impact on DDR3L memory interface
  DesignCon 2014: Where the Chip Meets the Board 2014
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• An efficient power integrity design methodology to prevent Platform failures for high density designs
  DesignCon 2013: Where Chipheads Connect 2013
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• Supply noise simulation and correlation for a multi-GHz high-speed serial link
  DesignCon 2013: Where Chipheads Connect 2013
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• Complete analysis and design of power integrity for advanced memory technology (DDR4)
  DesignCon 2012: Where Chipheads Connect 2012
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• Power grid parasitic impact on system level power delivery
  DesignCon 2012: Where Chipheads Connect 2012
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• Variables affecting the ultra low impedance PDN characterization
  DesignCon 2011 2011
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• Supply noise and jitter for multi-GT/s single-ended interface
  DesignCon 2011 2011
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• Reduced circuit modeling of mother board and package for a system power delivery analysis
  2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011 2011 DOI: 10.1109/EPEPS.2011.6100241
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