Sourav Guha

About

Sourav Guha has completed his Master's in VLSI Design and Microelectronics Technology (Electronics and Telecommunication Engineering) from Jadavpur University, India in 2020 and is a recipient of the Gold Medal for being the topper in his stream. His research is primarily focused on the modeling and low-power circuit implementation of novel nanoelectronic devices. His recent research interests include Negative-capacitance (ferroelectric)Tunnel-FET and III-V heterojunction semiconductor devices.

Employment

• Indian Institute of Science Bangalore PhD Scholar
  2024 - Present

Education

• Jadavpur University M.Tech
  2017 - 2020

Projects & Funding

Projects & funding information is unavailable.

Publications (6)

• Digital discovery of distorted-P1 molybdenum ditelluride and its significance in resistive switching
  Journal of Applied Physics 2026 DOI: 10.1063/5.0315066
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• Analytical Modelling of Dopingless (DL) Impact Ionization MOSFET (IMOS)
  Silicon 2022 DOI: 10.1007/s12633-022-01882-6
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• Design and Analog/RF Performance Analysis of a Novel Symmetric Raised-Channel SiGe Heterojunction Tunnel Field-Effect Transistor (TFET)
  Silicon 2022 DOI: 10.1007/s12633-021-01113-4
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• Heterojunction Negative-Capacitance Tunnel-FET as a Promising Candidate for Sub-0.4V VDD Digital Logic Circuits
  IEEE Transactions on Nanotechnology 2021 DOI: 10.1109/tnano.2021.3096252
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• Analytical model of a novel double gate metal-infused stacked gate-oxide tunnel field-effect transistor (TFET) for low power and high-speed performance
  Superlattices and Microstructures 2020 DOI: 10.1016/j.spmi.2020.106657
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• Effect of Body Thickness on Device Performance of Graded Channel Tri-Metal Double Gate Stack Gate TFET
  DOI: 10.1109/VLSIDCS47293.2020.9179899
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