Sudhanshu Janwadkar

Employment

• Nirma University of Science and Technology

Education

• Sardar Vallabhbhai National Institute of Technology Surat Doctorate of Philosophy
  2018 - 2024

Projects & Funding

Projects & funding information is unavailable.

Publications (14)

• Approximate Vedic Multiplier Based Digital Filter Architecture for Portable Biomedical Signal Acquisition
  Circuits, Systems, and Signal Processing 2026 DOI: 10.1007/s00034-025-03387-0
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• ASIC design of power and area efficient programmable FIR filter using optimized Urdhva-Tiryagbhyam Multiplier for impedance cardiography
  Microprocessors and Microsystems 2024 DOI: 10.1016/j.micpro.2024.105048
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• ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier
  International Journal of Circuit Theory and Applications 2024 DOI: 10.1002/cta.3844
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• XOR-Free Approach Towards Realization of Low Pass FIR Filter in Bio-Medical Signal Acquisition : Vedic Multiplier-based ASIC Implementation
  2023 IEEE 20th India Council International Conference (INDICON) 2023 DOI: 10.1109/indicon59947.2023.10440759
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• Power and Area Efficient FIR Filter Architecture in Digital Encephalography Systems
  e-Prime - Advances in Electrical Engineering, Electronics and Energy 2023 DOI: 10.1016/j.prime.2023.100148
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• Investigation and Analysis of Power Performance Area (PPA) Cards of Digital Multiplier Architectures
  Journal of Circuits, Systems and Computers 2022 DOI: 10.1142/S0218126622502395
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• Qualitative and Quantitative Analysis of Parallel-Prefix Adders
  Lecture Notes in Electrical Engineering 2021 DOI: 10.1007/978-981-15-6229-7_6
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• Strategic Design and Optimization of Vedic Low Pass FIR Filter for ECG Signals
  Lecture Notes in Electrical Engineering 2021 DOI: 10.1007/978-981-16-0275-7_1
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• Strategic Reduction of Area and Power in FIR Filter Architecture for ECG Signal Acquisition
  2020 IEEE 17th India Council International Conference (INDICON) 2020 DOI: 10.1109/indicon49873.2020.9342386
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• Implementation and Performance Evaluation of Novel Line Adder Architecture for Portable Systems : A Vedic Mathematics Approach
  2020 IEEE REGION 10 CONFERENCE (TENCON) 2020 DOI: 10.1109/tencon50793.2020.9293799
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