TITU MARY IGNATIUS

Employment

• Saraswati College of Engineering Assistant Professor
  2017 - 2018
• Model Engineering College Lecturer
  2010 - 2011
• Wipro (India) Project Engineer (VLSI),
  2008 - 2010

Education

• IIT Guwahati Phd
  2020 - 2025

Projects & Funding

Projects & funding information is unavailable.

Publications (15)

• Securing RISC-V SoC With Random Clock Self Complementary Countermeasure
  IEEE Embedded Systems Letters 2026 DOI: 10.1109/LES.2025.3567317
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• Low-Overhead Power Side-Channel Resistant AES Accelerator for RISC-V via Stall-Induced Trace Desynchronization and Activity Equalization
  IEEE Transactions on Circuits and Systems II: Express Briefs 2026 DOI: 10.1109/TCSII.2026.3720299
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• Securing RISC-V with Randomized Clock Countermeasure against PAA
  Semiconductor Research Cooperation (SRC) TECHCON 2025, Austin, Texas,USA 2025
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• RAESC: A Reconfigurable AES Countermeasure Architecture for RISC-V With Enhanced Power Side-Channel Resilience
  IEEE Computer Architecture Letters 2025 DOI: 10.1109/LCA.2025.3595003
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• Boosting AES Intrinsic Resilience Using Split SubBytes Round Function Against Power Attacks
  IEEE Embedded Systems Letters 2025 DOI: 10.1109/LES.2024.3420226
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• Non-Linear Cyclic Variable Clock Feistel Bridge-Inspired Countermeasure for Securing RISC-V Crypto-Core Against Power Attacks
  IEEE Transactions on Circuits and Systems I: Regular Papers 2025 DOI: 10.1109/TCSI.2025.3536284
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• Novel PRNG Design with Seed Updation Policy Using Fibonacci Sequence Generator
  Lecture Notes in Electrical Engineering 2025 DOI: 10.1007/978-981-96-3758-4_28
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• Improvement in Resilience of AES Design With Reconfigured CFB Mode Against Power Attacks
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2024 DOI: 10.1109/TVLSI.2024.3422501
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• Impact of Pipelining on Low Power IoT applicable RISC-V ISA Core Micro-architectures
  2024 IEEE 17th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC) 2024 DOI: 10.1109/MCSoC64144.2024.00045
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• Power Side-Channel Attacks on Crypto-Core Based on RISC-V ISA for High-Security Applications
  IEEE Access 2024 DOI: 10.1109/ACCESS.2024.3477961
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