Daichi Fujiki

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Publications (36)

• AQPIM: Breaking the PIM Capacity Wall for LLMs with in-Memory Activation Quantization
  2026 IEEE International Symposium on High Performance Computer Architecture (HPCA) 2026 DOI: 10.1109/hpca68181.2026.11408452
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• Efficient Vision Transformers via Token Merging with Head-wise Attention Correction
  Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision 2026
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• Memory-Efficient and Trustworthy Neural Networks via Random Seed-Based Design
  IEEE Access 2026 DOI: 10.1109/ACCESS.2026.3659474
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• BingoGCN: Towards Scalable and Efficient GNN Acceleration with Fine-Grained Partitioning and SLT
  2025 DOI: 10.1145/3695053.3731115
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• DX100: Programmable Data Access Accelerator for Indirection
  2025 DOI: 10.1145/3695053.3731015
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• TTF-GNN: Memory-Efficient GNNs via Tensor Train Decomposition and Network Folding
  2025 IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL CHIPS) 2025 DOI: 10.1109/coolchips65488.2025.11018558
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• Multi-Dimensional Vector ISA Extension for Mobile In-Cache Computing
  2025 IEEE International Symposium on High Performance Computer Architecture (HPCA) 2025 DOI: 10.1109/hpca61900.2025.00045
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• DMSA: An Efficient Architecture for Sparse–Sparse Matrix Multiplication Based on Distribute-Merge Product Dataflow
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2025 DOI: 10.1109/TVLSI.2025.3558895
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• SharK: Enabling High-Performance Range Queries in Key-Value Store Through Vlog Resharding
  IEEE Access 2025 DOI: 10.1109/ACCESS.2025.3638766
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• WhiteDwarf: A Holistic Co-Design Approach to Ultra-Compact Neural Inference Acceleration
  IEEE Access 2025 DOI: 10.1109/ACCESS.2025.3568916
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• WhiteDwarf: 12.24 TFLOPS/W 40 nm Versatile Neural Inference Engine for Ultra-Compact Execution of CNNs and MLPs Through Triple Unstructured Sparsity Exploitation and Triple Model Compression
  2024 IEEE Asian Solid-State Circuits Conference (A-SSCC) 2024 DOI: 10.1109/a-sscc60305.2024.10849314
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• OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configuration
  Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 2024 DOI: 10.1109/ASP-DAC58780.2024.10473966
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• Partial Search in a Frozen Network is Enough to Find a Strong Lottery Ticket
  arXiv preprint arXiv:2402.14029 2024
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• Restricted Random Pruning at Initialization for High Compression Range
  Transactions on Machine Learning Research 2024
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• MVC: Enabling Fully Coherent Multi-Data-Views through the Memory Hierarchy with Processing in Memory
  2023 DOI: 10.1145/3613424.3623784
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• HALO-CAT: A Hidden Network Processor with Activation-LOcalized CIM Architecture and Layer-Penetrative Tiling
  arXiv 2023 DOI: 10.48550/arXiv.2312.06086
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• Vector-Processing for Mobile Devices: Benchmark and Analysis
  Proceedings - 2023 IEEE International Symposium on Workload Characterization, IISWC 2023 2023 DOI: 10.1109/IISWC59245.2023.00036
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• Efficient placement of coherence directories in memory networks
  IEICE Technical Report; IEICE Tech. Rep. 2022
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• In-Memory Acceleration for General Data Parallel Applications
  2022
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• Multi-Layer In-Memory Processing
  Proceedings of the Annual International Symposium on Microarchitecture, MICRO 2022 DOI: 10.1109/MICRO56248.2022.00068
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