Bal Chand Nagar

About

Bal Chand Nagar is currently working as an Assistant Professor in the Department of Electronics and Communication Engineering, NIT Patna, Bihar, India. He did his B.E. (ECE) from MIT Mandsaur (RGPV, Bhopal), MP, India, M.Tech. (Microelectronics & VLSI Design) from SGSITS Indore (RGPV, Bhopal), MP, India, and Ph.D. from IIT(ISM) Dhanbad, JH, India. He has served, SVCE Indore, AITR Indore in various capacities. His research interests include Analog/RF and Digital Integrated Circuit Design, Signal processing circuits using analog building blocks, FPGA based System Design and Microelectronics Devices. He has published papers in International, National Journals of repute and conferences. He is a life member of IETE, ISTE, and IEI.

Employment

• National Institute of Technology Patna Assistant Professor
  2017 - Present

Education

• Indian Institute of Technology (Indian School of Mines), Dhanbad Ph.D.
  2013 - 2018
• Shri G. S. Institute of Technology & Science (SGSITS) M.Tech.
  2008 - 2010

Projects & Funding

Projects & funding information is unavailable.

Publications (33)

• EIISAA: energy-efficient instantaneous input-aware segmentation based error optimized approximate adder for error resilient applications
  Engineering Research Express 2026 DOI: 10.1088/2631-8695/ae95ba
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• TAARBM: A Truncated Adaptive Approximate Radix-8 Booth Multiplier for Image Processing Applications
  Micro and Nanosystems 2026 DOI: 10.2174/0118764029361847250810175040
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• MBTC: Memristor-MOS-Based Binary to Ternary Converter for Image Processing Application
  Journal of Circuits, Systems and Computers 2026 DOI: 10.1142/S0218126625300107
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• Analog Multiplier/Divider Using DXCCII with Fully Independent Device Parameters and Their Applications
  Journal of Circuits, Systems and Computers 2026 DOI: 10.1142/S0218126626501586
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• Realization of Electronically Tunable Dual-Memelement Emulator using FTFN and OTA
  Journal of Circuits, Systems and Computers 2025 DOI: 10.1142/S0218126625502676
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• LHCA: a new low-power, high-speed carry skip adder using hybrid memristor-MOS logic
  Discover Electronics 2025 DOI: 10.1007/s44291-025-00065-y
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• New FTFNTA-based tunable charge-controlled memristance simulator and its mutation to floating flux-controlled memristor emulator
  Analog Integrated Circuits and Signal Processing 2025 DOI: 10.1007/s10470-025-02402-3
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• Low-Power High-Speed Neuromorphic Integrated Circuits
  2025 DOI: 10.4018/979-8-3693-8084-0.ch008
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• SIEAA: Significant input extraction-based error optimized approximate adder for error resilient application
  Integration 2025 DOI: 10.1016/j.vlsi.2024.102317
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• Design and Implementation of Multifunctional Logic Circuits Using SRAM Cells Utilizing In-Memory Computing Concept
  2025 DOI: 10.1007/978-981-97-3090-2_7
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