Saurabh Khandelwal
Oxford Brookes University, ITM Group of Institutions, ITM University, ShriRam Group of Colleges
About
received the B.E. degree in electronics and communication and M. Tech degree in VLSI design from Rajiv Gandhi Technical University, Bhopal, India in the year 2005 and 2011 respectively. He has been awarded Ph.D. from ITM University, Gwalior, India in the year 2016. He served as an Assistant Professor with the department of electronics and communication, ITM Group of Institution, Gwalior, India. He is currently a post-doctoral research fellow with the Department of Computing and Communication Technologies, Oxford Brookes University, Oxford, UK in the Advanced Reliable Computer Systems Group. Mr. Khandelwal has authored/co-authored more than 45 research papers. His research papers have been published in various peer reviewed National/International Journals including those enlisted in the Thomson Reuters List of Journals, and Conferences including 27th, 28th and 29th M.P. Young Scientist Congress. In April 2012, Mr. Khandelwal submitted an oral presentation in an international conference namely 2nd International Advances in Applied Physics and Materials Science Congress (APMAS 2012) held at Antalya, Turkey. The Department of Science and Technology, Government of India had provided international travel support to Mr. Khandelwal for the conference. In July 2013, Mr. Khandelwal has undertaken an International Advance Training - ipv6 Infrastructure Security for Telecom Networks held at Bangkok, Thailand which was organized by the International Telecommunication Union and Government of Thailand. Madhya Pradesh Council of Science and Technology, Government of Madhya Pradesh, had provided international travel support to Mr. Khandelwal for the training. In February 2014, Mr. Khandelwal received Young Scientist award by M.P. Council of Science and Technology, Government of Madhya Pradesh, India. Recently in April 2015, Mr. Khandelwal received Young Outstanding Person Award by the JC International Gwalior. His biography published in Marquis’s Who’s Who in Engineering Field, USA awarded by Marquis, 2015. In 2016, he has been shortlisted for the India TR 35 award for the year 2016 (Young Innovator Award from MIT Technology Review 35). In the same year, Mr. Khandelwal has been the recipient of the Cambridge Certificate (The International Biographical Center “CAMBRIDGE CERTIFICATE” for Outstanding Engineering Achievement and also the recipient of the “GWALIOR GAURAV” by Gwalior Vikas Samiti, Gwalior. Mr. Khandelwal has also been honored by Lions Club, Gwalior. Mr. Khandelwal is a reviewer of various renowned Journals cited by Science Citation Index, Scopus etc. He is also a life member of Indian Science Congress, Government of India. His current research interests include digital VLSI circuit design, electronic design automation, computer architectures, reliable and error-tolerant digital systems, in particular, emerging technologies.
Employment
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Oxford Brookes University Research Associate2018 - Present
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ITM Group of Institutions Assistant Professor2016 - Present
Education
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ITM University PhD (Doctor of Philosophy) / ANALYSIS AND OPTIMIZATION OF NANOSCALE FINFET BASED LOW POWER SRAM CELL2012 - 2016
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ITM Group of Institutions M.Tech (Masters of Technology) / VLSI Design2009 - 2011
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ShriRam Group of Colleges B.E. (Bachelor of Engineering) / Electronics and Communication Engineering2005 - 2009
Projects & Funding
Projects & funding information is unavailable.
Publications (68)
- A low overhead chemical measurement architecture with memristive sensors Save
- Low power memristive gas sensor architectures with improved sensing accuracy Save
- 45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control Save
- Fault Modeling and Simulation of Memristor based Gas Sensors Save
- Secure memristor replicator architecture with physical uncloneability Save
- The Missing Applications Found: Robust Design Techniques and Novel Uses of Memristors Save
- Impact of NBTI on 8T FinFET based SRAM cell Save
- Implementation of leakage reduction techniques in finfet based 3T DRAM based at 45 nm technology Save
- Simulation and Verification of LECTOR 6T FinFET SRAM: A Low Leakage Cell Save
- Design and Implement 1 Kb Array Employing Low-Power Low-Voltage 3T Gain-Cell Memory at 45 nm Scheme Save