Vinay B. Y. Kumar

Employment

• Asustek Computer Inc Senior Engineer
  2008 - 2011
• Imec Researcher
• Nanyang Technological University Postdoctoral Research Fellow

Education

• Indian Institute of Technology Bombay B. Tech
  2003 - 2008
• Indian Institute of Technology Bombay M. Tech
  2003 - 2008
• Indian Institute of Technology Bombay Ph. D

Projects & Funding

Projects & funding information is unavailable.

Publications (17)

• AERO: Design Space Exploration Framework for Resource-Constrained CNN Mapping on Tile-Based Accelerators
  IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2022 DOI: 10.1109/JETCAS.2022.3171826
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• Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault Attacks
  Design, Automation & Test in Europe Conference & Exhibition (DATE) 2021 DOI: 10.23919/DATE51398.2021.9474072
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• Towards Designing a Secure RISC-V System-on-Chip: ITUS
  Journal of Hardware and Systems Security 2020 DOI: 10.1007/s41635-020-00108-8
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• Post-Quantum Secure Boot
  2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) 2020 DOI: 10.23919/date48585.2020.9116252
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• A Novel Duplication Based Countermeasure to Statistical Ineffective Fault Analysis
  Information Security and Privacy 2020 DOI: 10.1007/978-3-030-55304-3_27
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• ITUS: A Secure RISC-V System-on-Chip
  International System on Chip Conference 2019 DOI: 10.1109/SOCC46988.2019.1570564307
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• Recruiting Fault Tolerance Techniques for Microprocessor Security
  Proceedings of the Asian Test Symposium 2019 DOI: 10.1109/ATS47505.2019.00015
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• Lightweight Forth Programmable NoCs
  Proceedings of the IEEE International Conference on VLSI Design 2018 DOI: 10.1109/VLSID.2018.92
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• Relaxation Based Circuit Simulation Acceleration over CPU-FPGA
  Proceedings of the IEEE International Conference on VLSI Design 2016 DOI: 10.1109/VLSID.2016.84
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• Framework for Application Mapping over Packet-Switched Network of FPGAs: Case Studies
  2015
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