B. Naresh Kumar Reddy
Also known as: Beechu Naresh Kumar Reddy
National Institute of Technology Tiruchirappalli, Indian Institute of Information Technology and Management, Kerala, K.L.University, Sri Venkateswara University
0000-0001-8434-3673
About
B. Naresh Kumar Reddy is an accomplished individual in the field of Electronics and Communication Engineering. With a strong educational background, including a B.Tech from Sri Venkateswara University, an M.Tech from K.L.University, and a Doctoral Degree from the National Institute of Technology Goa, he has gained extensive knowledge in his field. He has gained practical experience through internships at Intel Technology India Pvt. Ltd. and as a Post-Doctoral Fellow at the Indian Institute of Technology Delhi. Currently serving as an Assistant Professor at the National Institute of Technology in Tiruchirappalli, Tamil Nadu, he is actively involved in teaching and research, focusing on areas such as Networks-on-Chip, VLSI system design, and Embedded Systems. His contributions are evident through his numerous publications in prestigious journals and conferences. As a Senior member of IEEE and a member of ACM, he continues to contribute to the advancement of FPGA field.
Employment
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National Institute of Technology Tiruchirappalli Assistant Professor2022 - Present
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Indian Institute of Information Technology and Management, Kerala Assistant Professor2021 - 2022
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Indian Institute of Technology Delhi, India. Post-Doctoral Fellow2020 - 2021
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ICFAI Tech Assistant Professor2018 - 2020
Education
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K.L.University M.Tech2010 - 2012
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Sri Venkateswara University2006 - 2010
Projects & Funding
Projects & funding information is unavailable.
Publications (98)
- Advanced task scheduling algorithm for enhanced energy efficiency on multi-core embedded platforms Save
- Enhanced performance of full adder using advanced 9-T XOR-XNOR module Save
- Energy-Efficient Multi-Precision Floating-Point Architecture for Unified AI and HPC Workloads Save
- Integrated gradients for explainable DQN-driven cognitive sensor fusion adaptive module selection for enhanced perception under realistic environmental degradations Save
- Analyzing Fully Depleted SOI NC‐MOSFET for Enhanced Bio‐Sensor and Digital Circuit Applications Save
- Design and Investigation of the 22 nm FinFET Based Dynamic Latched Comparator for Low Power Applications Save
- Optimizing Task Scheduling in Multi-thread Real-Time Systems using Augmented Particle Swarm Optimization Save
- Evaluating the effectiveness of Bat optimization in an adaptive and energy-efficient network-on-chip routing framework Save
- Enhanced PSO-Integrated Machine Learning for Launch Vehicle Engine Temperature and Pressure Monitoring for Risk Prediction Save
- An Area-Efficient VLSI Architecture with Ladner-Fischer PPA for High-Speed Pseudo-Random Bit Generation Save