Shantharam Kalipatnapu

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Publications (3)

• High speed VLSI architecture for improved region based active contour segmentation technique
  Integration 2021 DOI: 10.1016/j.vlsi.2020.11.004
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• Low-Complexity Interval Passing Algorithm and VLSI Architecture for Binary Compressed Sensing
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2020 DOI: 10.1109/TVLSI.2020.2967477
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• High-throughput bit flipping decoder for structured LDPC codes
  IET Communications 2019 DOI: 10.1049/iet-com.2019.0229
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