Avaneesh K. Dubey

About

Avaneesh Kumar Dubey received the Ph.D. degree from Motilal Nehru National Institute of Technology (MNNIT) Allahabad in 2019, the M.Tech. degree from Atal Bihari Vajpayee–Indian Institute of Information Technology and Management (ABV‑IIITM), Gwalior, in 2015, and the B.Tech. degree in Electronics and Communication Engineering from Gautam Buddh Technical University (GBTU), Lucknow.
He is currently working as a Staff Solutions Engineer at Synopsys. His research interests include low‑power VLSI design and mixed‑signal signal processing.

Employment

• Synopsys (India) Pvt. Ltd.
  2023 - Present
• Aditya Engineering College Assistant Professor
  2022 - 2023
• Motilal Nehru National Institute of Technology Temporary Faculty
  2019 - 2022

Education

Education history is unavailable.

Projects & Funding

Projects & funding information is unavailable.

Publications (14)

• Design and Analysis of Noise Immune, Energy Efficient 1-bit 8T SRAM Cell
  2023 DOI: 10.1007/978-981-99-0973-5_35
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• Low-power high-speed CMOS double tail dynamic comparator using self-biased amplification stage and novel latch stage
  Analog Integrated Circuits and Signal Processing 2019 DOI: 10.1007/s10470-019-01518-7
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• Design and Analysis of an Energy-Efficient High-Speed CMOS Double-Tail Dynamic Comparator with Reduced Kickback Noise Effect
  Journal of Circuits, Systems and Computers 2019 DOI: 10.1142/S0218126619501573
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• A High-Speed Energy-Efficient CMOS Dynamic Latch Comparator for Low-Voltage Applications
  Proceedings - 2019 International Conference on Electrical, Electronics and Computer Engineering, UPCON 2019 2019 DOI: 10.1109/UPCON47278.2019.8980209
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• Design and performance of high-speed low-offset CMOS double-tail dynamic comparators using offset control scheme
  IEMECON 2019 - 9th Annual Information Technology, Electromechanical Engineering and Microelectronics Conference 2019 DOI: 10.1109/IEMECONX.2019.8876979
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• Impact of channel doping fluctuation and metal gate work function variation in FD-SOI MOSFET for 5nm BOX Thickness
  2019 IEEE Conference on Information and Communication Technology, CICT 2019 2019 DOI: 10.1109/CICT48419.2019.9066255
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• Enhanced Gain Low-Power CMOS Amplifiers: A Novel Design Approach Using Bulk-Driven Load and Introduction to GACOBA Technique
  Journal of Circuits, Systems and Computers 2018 DOI: 10.1142/S0218126618502043
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• Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load
  Microelectronics Journal 2018 DOI: https://doi.org/10.1016/j.mejo.2018.05.006
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• A Modified High Speed Domino with Low Leakage for Wide Fan-in Domino OR-Gate
  INDICON 2018 - 15th IEEE India Council International Conference 2018 DOI: 10.1109/INDICON45594.2018.8987072
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• Design of power efficient low-offset dynamic latch comparator using 90nm CMOS process
  3rd International Conference on Innovative Applications of Computational Intelligence on Power, Energy and Controls with their Impact on Humanity, CIPECH 2018 2018 DOI: 10.1109/CIPECH.2018.8724234
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