Dr. Kamalaksha Baral

Employment

• VIT-AP Campus Assistant Professor
  2021 - Present

Education

Education history is unavailable.

Projects & Funding

Projects & funding information is unavailable.

Publications (47)

• GaSb/GaAs Type-II Heterojunction TFET on SELBOX Substrate for Dielectric Modulated Label-Free Biosensing Application
  IEEE Transactions on Electron Devices 2022 DOI: 10.1109/TED.2022.3191295
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• A unified 2-D model for nanowire junctionless accumulation and inversion mode MOSFET in quasi-ballistic regime
  Solid-State Electronics 2022 DOI: 10.1016/j.sse.2022.108282
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• Performance Optimization of ZnO Nanorods ETL Based Hybrid Perovskite Solar Cells With Different Seed Layers
  IEEE Transactions on Electron Devices 2022 DOI: 10.1109/TED.2022.3162552
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• Comparative Analysis and Performance Optimization of Low-Cost Solution-Processed Hybrid Perovskite-Based Solar Cells With Different Organic HTLs
  IEEE Transactions on Electron Devices 2022 DOI: 10.1109/TED.2022.3194106
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• Analytical Drain Current Model for Source Pocket Engineered Stacked Oxide SiO<inf>2</inf>/HfO<inf>2</inf> Cylindrical Gate TFETs
  Silicon 2021 DOI: 10.1007/s12633-020-00563-6
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• Impact of interface trap charges on electrical performance characteristics of a source pocket engineered Ge/Si heterojunction vertical TFET with HfO<inf>2</inf>/Al<inf>2</inf>O<inf>3</inf> laterally stacked gate oxide
  Microelectronics Reliability 2021 DOI: 10.1016/j.microrel.2021.114073
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• Impact of ion implantation on stacked oxide cylindrical gate junctionless accumulation mode MOSFET: An electrical and circuit level analysis
  Materials Science in Semiconductor Processing 2021 DOI: 10.1016/j.mssp.2021.105966
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• III-V/Si staggered heterojunction based source-pocket engineered vertical TFETs for low power applications
  Superlattices and Microstructures 2020 DOI: 10.1016/j.spmi.2020.106494
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• Performance Comparison of Ge/Si Hetero-Junction Vertical Tunnel FET with and without Gate-Drain Underlapped Structure with Application to Digital Inverter
  4th Electron Devices Technology and Manufacturing Conference, EDTM 2020 - Proceedings 2020 DOI: 10.1109/EDTM47692.2020.9117840
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• Impact of heterogeneous gate dielectric on DC, RF and circuit-level performance of source-pocket engineered Ge/Si heterojunction vertical TFET
  Semiconductor Science and Technology 2020 DOI: 10.1088/1361-6641/aba418
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