sudha vani

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Publications (8)

• Design an energy efficient ternary parallel prefix carry/sum propagate adders using 32-nm CNTFET
  Memories - Materials, Devices, Circuits and Systems 2025 DOI: 10.1016/j.memori.2025.100129
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• Area Efficient Sparse-4 Diminished-1 Modulo 2n+ 1 Adder
  2024 IEEE Wireless Antenna and Microwave Symposium Wams 2024 2024 DOI: 10.1109/WAMS59642.2024.10527894
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• Design an energy efficient pulse triggered ternary flip flops with Pseudo NCFET logic
  Analog Integrated Circuits and Signal Processing 2024 DOI: 10.1007/s10470-023-02236-x
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• An Energy-Efficient Hybrid Tunnel FET based STT-MRAM Memory Cell Design at Low VDD
  International Journal of Electronics 2022 DOI: 10.1080/00207217.2021.1914191
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• Design of Three Stage Dynamic Comparator with Tail Transistor using 20nm FinFET Technology for ADCs
  Proceedings 2022 International Conference on Computing Communication and Power Technology Ic3p 2022 2022 DOI: 10.1109/IC3P52835.2022.00016
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• A 128Kb RAM design with capacitor-based offset compensation and double-diode based read assist circuits at low vDD
  Journal of Scientific and Industrial Research 2020
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• A low voltage capacitor based current controlled sense amplifier for input offset compensation
  Proceedings International Soc Design Conference 2017 Isocc 2017 2018 DOI: 10.1109/ISOCC.2017.8368810
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• Carbon nano tube field effect transistors based ternary Ex-OR and Ex-NOR gates
  Current Nanoscience 2016 DOI: 10.2174/1573413712666151216221629
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