Sandeep Dhariwal

Employment

• Alliance University Associate Professor
  2018 - Present

Education

Education history is unavailable.

Projects & Funding

Projects & funding information is unavailable.

Publications (31)

• Design and analysis of 1-bit hybrid full adder cells for fast computation
  International Journal of Electronics 2024 DOI: 10.1080/00207217.2024.2361931
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• Charge Transport in Semiconductor Heterogeneous Structure at Oxide Interface by Inserting a Functional Layer
  2024 International Conference on Wireless Communications, Signal Processing and Networking, WiSPNET 2024 2024 DOI: 10.1109/WiSPNET61464.2024.10533100
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• Design and Analysis of Low Power MAC for DSP Processor
  2023 International Conference on Artificial Intelligence and Applications, ICAIA 2023 and Alliance Technology Conference, ATCON-1 2023 - Proceeding 2023 DOI: 10.1109/ICAIA57370.2023.10169461
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• Low Power Full Adders based on Proposed Hybrid and GDI Designs: A Novel Approach
  International Journal of Performability Engineering 2023 DOI: 10.23940/ijpe.23.03.p2.167174
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• Preface
  2023 International Conference on Artificial Intelligence and Applications, ICAIA 2023 and Alliance Technology Conference, ATCON-1 2023 - Proceeding 2023 DOI: 10.1109/ICAIA57370.2023.10169172
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• Damage Identification of Beam Structure Using Discrete wavelet transform
  2022 2nd International Conference on Artificial Intelligence and Signal Processing, AISP 2022 2022 DOI: 10.1109/AISP53593.2022.9760606
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• Hybrid GDI PTL Full Adder: A Proposed Design for Low Power Applications
  International Journal of Performability Engineering 2022 DOI: 10.23940/ijpe.22.01.p3.2229
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• Next-gen traffic rule violation detection using optimum feature extraction techniques on highway and toll tax using Raspberry-pi hardware
  2022 2nd International Conference on Artificial Intelligence and Signal Processing, AISP 2022 2022 DOI: 10.1109/AISP53593.2022.9760531
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• Delay reduction by implementation of voltage-controlled ring oscillator with reverse substrate bias
  International Journal of Performability Engineering 2020 DOI: 10.23940/ijpe.20.03.p1.325332
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• Design and analysis of power and area efficient novel concurrent cellular automation logic block observer BIST structure
  International Journal of Performability Engineering 2020 DOI: 10.23940/ijpe.20.01.p3.1926
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