Shreeharsha K G

Employment

• Manipal Academy of Higher Education Teaching
  2011 - Present

Education

• NMAM Institute of Technology M.Tech
  2008 - 2010

Projects & Funding

Projects & funding information is unavailable.

Publications (11)

• A Power-Efficient High-Speed D-Latch Architecture for Enhanced PDP Performance
  IEEE Access 2026 1 citation DOI: 10.1109/ACCESS.2026.3683583
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• MFDFA-Enhanced GAN: A Hardware-Optimized Architecture for Efficient Synthetic Image Generation
  IEEE Access 2026 0 citations DOI: 10.1109/ACCESS.2026.3677066
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• An energy-efficient D-latch architecture with feedforward technique for high-speed applications
  Results in Engineering 2025 0 citations DOI: 10.1016/j.rineng.2025.107301
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• Evolutionary-Enhanced GAN With Wavelet-Based Discrimination: A Hardware-Accelerated Architecture for Efficient Synthetic Image Generation
  IEEE Access 2025 0 citations DOI: 10.1109/ACCESS.2025.3642041
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• Generating Synthetic Data Using 2D Multifractal Detrended Fluctuation Analysis Generative Adversarial Networks
  IEEE Access 2025 0 citations DOI: 10.1109/ACCESS.2025.3603332
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• An exponential variation based PSO for analog circuit sizing in constrained environment
  AEU - International Journal of Electronics and Communications 2024 4 citations DOI: 10.1016/j.aeue.2024.155531
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• An Error Bound Particle Swarm Optimization for Analog Circuit Sizing
  IEEE Access 2024 7 citations DOI: 10.1109/ACCESS.2024.3385491
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• N-Parallel Paths-Based D-Latch for High-Speed Applications
  IEEE Access 2024 4 citations DOI: 10.1109/ACCESS.2024.3491577
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• RTL to GDSII Implementation of RADIX-4 Booth Multiplier using Opensource EDA tools
  2023 1st International Conference on Circuits, Power and Intelligent Systems (CCPIS) 2023 3 citations DOI: 10.1109/ccpis59145.2023.10291665
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• Partition Bound Random Number-Based Particle Swarm Optimization for Analog Circuit Sizing
  IEEE Access 2023 7 citations DOI: 10.1109/ACCESS.2023.3329698
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