Vivek Saraswat

About

Vivek Saraswat received dual B. Tech. and M. Tech. degrees in Electrical Engineering with specialization in microelectronics from the Indian Institute of Technology Bombay (India) in 2018. He received the Undergraduate Research Award for his dual degree thesis on network applications of resistive switching devices. He was selected for the Prime Minister’s Research Fellowship to continue quality research at IIT Bombay, where he is also pursuing a Ph. D. degree in the Department of Electrical Engineering under the guidance of Prof. Udayan Ganguly. He has submitted his Ph. D. thesis on the modelling and control of PCMO-based RRAM in 2023.

He has worked on emerging memories for in-memory computing, on-chip training for SRAM-based ANN, and probabilistic neural networks using stochastic devices as a part of the India Research Program of the Semiconductor Research Corporation, from 2019 to 2022. He was a part of Intel’s Neuromorphic Research Community to benchmark Speech Classification algorithms using LSM on Intel’s Loihi from 2018 to 2022. His research interest includes memory devices for neuromorphic applications, and network architectures and algorithms for classification and optimization. He has authored/co-authored 8 journal papers and 14 conference articles and applied 6 patents till 2022. He has been a teaching assistant for 10 semesters at IIT Bombay, Gandhinagar and Varanasi in courses ranging from nanoelectronics, device physics, VLSI technology and neuromorphic engineering.

Employment

Employment history is unavailable.

Education

• Indian Institute of Technology Bombay B. Tech + M. Tech Dual Degree
  2013 - 2018

Projects & Funding

Projects & funding information is unavailable.

Publications (32)

• One-Time Programmable Memory for Ultra-Low Power ANN Inference Accelerator With Security Against Thermal Fault Injection
  IEEE Journal of the Electron Devices Society 2025 DOI: 10.1109/JEDS.2024.3508759
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• Analog and Temporary On-chip Memory for ANN Training and Inference
  ACM Journal on Emerging Technologies in Computing Systems 2025 DOI: 10.1145/3765899
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• FeFET-Based MirrorBit Cell for High-Density NVM Storage
  IEEE Transactions on Electron Devices 2024 DOI: 10.1109/TED.2024.3361843
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• Schottky Barrier MOSFET Enabled Ultra-Low Power Real-Time Neuron for Neuromorphic Computing
  2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) 2023 DOI: 10.1109/edtm55494.2023.10103118
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• Robustness to Variability and Asymmetry of In-Memory On-Chip Training
  2023 DOI: 10.1007/978-3-031-44201-8_21
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• Vector-Matrix-Multiplication Acceleration with Multi-Input Pr0.7Ca0.3MnO3 based RRAM for Highly Parallel In-Memory Computing
  2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) 2023 DOI: 10.1109/edtm55494.2023.10103016
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• ANN Inference enabled by Variability Mitigation using 2T-1R Bit Cell-based Design Space Analysis
  2023 IEEE International Symposium on Circuits and Systems (ISCAS) 2023 DOI: 10.1109/iscas46773.2023.10181912
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• Real-world Performance Estimation of Liquid State Machines for Spoken Digit Classification
  2023 International Joint Conference on Neural Networks (IJCNN) 2023 DOI: 10.1109/ijcnn54540.2023.10191451
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• Optimizing Throughput and Latency of Static 5G Multicast Networks using Boltzmann Machines
  2023 International Joint Conference on Neural Networks (IJCNN) 2023 DOI: 10.1109/ijcnn54540.2023.10191207
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• Enhanced regularization for on-chip training using analog and temporary memory weights
  Neural Networks 2023 DOI: 10.1016/j.neunet.2023.07.001
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