jiaxin liu

About

Jiaxin Liu is currently a Post-Doctoral Researcher with Department of Electrical Engineering, Tsinghua University, Beijing, China.

He received the B.S. degree from Shandong University, Jinan, China, in 2010, and the M.S. and Ph.D. degrees from the University of Electronic Science and Technology of China (UESTC), Chengdu, China, in 2013 and 2018, respectively. From 2015 to 2017, he was a Joint Ph.D. Student with the University of Texas (UT) at Austin, Austin, TX, USA.

He was a recipient of the First Prize of Academic Scholarship in UESTC for the consecutive years from 2012 to 2015, the China National Scholarship in 2012, the First Prize of VeriSilicon Circuits Design Competition in 2015, and the China CSC Scholarship in 2015.

His research interest is on analog and mixed-signal integrated circuits design, with special focus on energy-efficient analog-to-digital conveters (ADCs).

Employment

• Tsinghua University
  2018 - Present

Education

• The University of Texas at Austin
  2015 - 2017
• University of Electronic Science and Technology of China
  2010 - Present

Projects & Funding

Projects & funding information is unavailable.

Publications (25)

• A 97.7-dB SNDR 179.3-dB FoMS Noise-Shaping SAR ADC With kT/C Noise Cancellation and Input Impedance Boosting for Biosignal Acquisition
  IEEE Transactions on Circuits and Systems I: Regular Papers 2026 DOI: 10.1109/TCSI.2026.3719453
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• A CDAC-Interleaved OTA-Free Fourth-Order Noise-Shaping SAR ADC With Twofold Passive Gain
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2026 DOI: 10.1109/TVLSI.2026.3701908
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• A 71.3 dB-SNDR Fully Passive Speed Enhanced 4× OSR Second-Order NS SAR ADC With Excessive-Capacitor-Reset Switching Scheme
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2026 DOI: 10.1109/TVLSI.2026.3686072
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• Analyses Concerning the Phase Noise and Nonlinear Behavior of the Charge-Sharing Integrator-Based Hybrid PLL
  IEEE Transactions on Circuits and Systems I: Regular Papers 2025 DOI: 10.1109/TCSI.2024.3508838
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• A 5-MS/s 93.4-dB-DR Three-Step Incremental Zoom ADC With Single Sampling
  IEEE Transactions on Circuits and Systems I: Regular Papers 2025 DOI: 10.1109/TCSI.2025.3539833
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• Analysis and Design of Noise-Shaping SAR ADC with Capacitor Stacking and Buffering
  Chips 2024 DOI: 10.3390/chips3040015
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• An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update
  IEEE Journal of Solid-State Circuits 2024 DOI: 10.1109/JSSC.2023.3324954
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• Mitigating Sampling Noise for Energy-Efficient ADCs: A Tutorial Brief
  IEEE Transactions on Circuits and Systems II: Express Briefs 2024 DOI: 10.1109/TCSII.2023.3337969
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• SAMBA: Single-ADC Multi-Bit Accumulation Compute-in-Memory Using Nonlinearity- Compensated Fully Parallel Analog Adder Tree
  IEEE Transactions on Circuits and Systems I: Regular Papers 2023 DOI: 10.1109/TCSI.2023.3266269
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• A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier
  IEEE Journal of Solid-State Circuits 2023 DOI: 10.1109/JSSC.2023.3268719
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