0000-0001-9788-6386 About
Aryan Kannaujiya completed a PhD in Electrical Engineering with specialization in Electrical Engineering (VLSI Design) from IIT Jammu. His research focuses on reliable and low-power CMOS integrated circuit design, including Schmitt trigger-based circuits, SRAM architectures, domino logic, sense amplifiers, and soft error resilient semiconductor systems. His work involves the design and analysis of energy-efficient and reliable CMOS circuits for advanced microelectronic applications.
His technical expertise includes Cadence Virtuoso, Synopsys, Mentor Graphics, Verilog, MATLAB, and CMOS layout design methodologies covering schematic design, simulation, physical layout, DRC/LVS verification, and tapeout implementation. He has experience in multiple semiconductor chip tapeouts, including Schmitt trigger-based logic circuits, SRAM architectures, and synchronous counter designs using standard CMOS technologies.
His research contributions have been recognized through Best Paper Awards at IEEE VDAT 2024 and IEEE VDAT 2025. He has also presented research work at international conferences including IEEE ICECS 2024, Nancy, France, and PRIME 2025, Valencia, Spain. His research activities are intended for academic, educational, and semiconductor research and development purposes.
Employment
Employment history is unavailable.
Education
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Indian Institute of Technology Jammu Ph.D2021 - Present
Projects & Funding
Projects & funding information is unavailable.
Publications (15)
- Enhanced soft error resilience of NBTI-tolerant dual mode Schmitt trigger circuit Save
- Radiation Effects in VLSI Circuits - Part II: Hardening Techniques Save
- Parallel Feedback Controlled Low-Power and Reliable Schmitt Trigger Circuit Save
- Radiation Hardened Domino Logic-Based Schmitt Trigger Circuit With Improved Noise Immunity Save
- Radiation Effects in VLSI Circuits – Part I: Historical Perspective Save
- Performance enhancement of OLED employing CuSCN interfacial layer Save
- Efficient THD Mitigation and Enhanced Output in Single-Phase 5-Level Inverters: A Variable Frequency PWM Approach Save
- Enhancing Noise Immunity of Schmitt Triggers through Dual PMOS Transistor Save
- High-Performance Cascoded CMOS LNA Configuration for Next-Gen Wireless Application Save
- Noninverting Schmitt Trigger Circuit with Improved Hysteresis Behavior Save