Dr. Lokenath Kundu

About

Dr. Lokenath Kundu is currently serving as a Senior Engineer in Analog RF Design at Silizium Circuits, Kochi, Kerala, where he is actively engaged in the design of Analog and mixed-signal circuits. He holds a PhD in Analogue IC Design from NIT Silchar (2025), with research focused on PLL. Prior to this, he completed his M.Tech in Microelectronics and VLSI Design from NIT Sikkim in 2020 and his B.Tech in Electrical Engineering from College of Engineering &Management, Kolaghat in 2013. His academic and professional journey reflects a strong background in high-speed and low-power VLSI design. He is the reviewer of some journal like Springer Nature (AICSP).

Employment

• Silizium Circuits Senior Engineer, Analog RF Design
  2024 - Present
• National Institute Of Technology Silchar Ph.D Research Scholar
  2020 - 2025

Education

• National Institute Of Technology Silchar Ph.D Research Scholar
  2020 - 2024
• National Institute of Technology Sikkim Masters Student
  2018 - 2020

Projects & Funding

Projects & funding information is unavailable.

Publications (9)

• Design and analysis of 5th order $$\textrm{G}_\textrm{m}$$– C filter with novel back-gate driven split-folded cascode (BG-SFC) OTA for application in the frontend of enhanced Parkinson’s disease detection
  Microsystem Technologies 2026 DOI: 10.1007/s00542-025-05992-0
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• A Design Approach of Multi-modulus CML Frequency Divider Using Delay Cell for Low-Power PLL Applications
  2026 DOI: 10.1007/978-981-92-0217-1_62
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• Design of a low-power, low-PDP dual modulus CML frequency divider for ZigBee application
  Integration 2025 DOI: 10.1016/j.vlsi.2025.102400
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• Design of CML-Based Odd Frequency Divider Using Delay Cell for Low-Power Application
  Journal of Circuits, Systems and Computers 2025 DOI: 10.1142/S0218126625501865
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• A Design Approach for ZigBee Compatible CML-based 2/3 Dual Modulus Frequency Divider
  VDAT-2024 2024 DOI: doi: 10.1109/VDAT63601.2024.10705715.
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• Design and Analysis of Cross-Coupled Source Degenerated Balanced OTA for Biomedical Application
  VDAT-2024 2024 DOI: doi: 10.1109/VDAT63601.2024.10705720
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• Analysis of a Low-Power OTA-Based Neural Amplifier Design for EEG Signal Acquisition
  Journal of Circuits, Systems and Computers 2024 DOI: 10.1142/S0218126624501743
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• A Divide-By-5 Pre-scaler Design Approach for 5G Applications
  Lecture Notes in Electrical Engineering 2022 DOI: 10.1007/978-981-16-3767-4_15
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• A Design Methodology of MOS Current Mode Logic Pre-Scaler for ZigBee Applications
  2021 International Conference on Advances in Technology, Management & Education (ICATME) 2021 DOI: 10.1109/icatme50232.2021.9732723
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