Rahul Bhattacharya

Employment

• Indian Institute of Technology Dhanbad Assistant Professor
  2013 - Present
• ST-Ericsson India Private Limited Senior Desgin Engineer
  2010 - 2013
• Indian Institute of Technology Kharagpur Research Consultant
  2006 - 2010
• Wipro (India) Project Engineer
  2005 - 2006

Education

• Indian Institute of Technology Kharagpur MS(by Research)
  2007 - 2012
• National Institute of Technology B.E
  2001 - 2005

Projects & Funding

Projects & funding information is unavailable.

Publications (17)

• Exploring Differential Evolution Algorithms in Search of Best Test Vector for Digital Circuit Testing
  Journal of Electronic Testing 2026 DOI: 10.1007/s10836-026-06217-6
  +Save
• Exploring Differential Evolution Algorithm with Fitness-and Position-Based Selection in Search of Best Test Pattern for Combinational ATPG
  2026 IEEE 10th International Test Conference India (ITC India) 2026 DOI: 10.1109/itcindia70344.2026.11646540
  +Save
• Single and Multiple Fault Detection in Analog Circuits Using V-Transform Coefficients
  2025 Devices for Integrated Circuit (DevIC) 2025 DOI: 10.1109/devic63749.2025.11012469
  +Save
• MATLAB-Simulink based Framework for Combinational ATPG Applied to Testing of Digital Blocks in Analog and Mixed-Signal Circuits
  2024 28th International Symposium on VLSI Design and Test (VDAT) 2024 DOI: 10.1109/vdat63601.2024.10705730
  +Save
• Fault Emulation in Digital Circuits using FPGA based Software-Hardware Co-Simulation
  2024 11th International Conference on Signal Processing and Integrated Networks (SPIN) 2024 DOI: 10.1109/spin60856.2024.10511916
  +Save
• Emulation of Nonlinear Dynamics of RF Power Amplifier on FPGA
  2024 IEEE 9th International Conference for Convergence in Technology (I2CT) 2024 DOI: 10.1109/i2ct61223.2024.10543698
  +Save
• MATLAB-Open Source Tool Based Framework for Test Generation for Digital Circuits Using Evolutionary Algorithms
  Journal of Electronic Testing 2023 DOI: 10.1007/s10836-023-06088-1
  +Save
• Fault diagnosis in switched‐linear systems by emulation of behavioral models on FPGA: A case study of current‐mode buck converter
  International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 2018 DOI: 10.1002/jnm.2314
  +Save
• Resource optimization for emulation of behavioral models of mixed signal circuits on FPGA: a case study of DC–DC buck converter
  International Journal of Circuit Theory and Applications 2017 DOI: 10.1002/cta.2323
  +Save
• SFG Based Fault Simulation of Linear Analog Circuits Using Fault Classification and Sensitivity Analysis
  2017 DOI: 10.1007/978-981-10-7470-7_19
  +Save