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Jai Gopal Pandey

Central Electronics Engineering Research Institute CSIR, Birla Institute of Technology and Science

ORCID iD 0000-0001-9937-7438
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About

Jai Gopal Pandey has received his M.Tech. degree in Electronics Design and Technology from U. P. Technical University, Lucknow, India, in 2003. He has obtained the Ph.D. degree in Electronics Engineering from Birla institute of technology and science (BITS), Pilani, India in 2015. He is with council of scientific and industrial research- central electronics engineering research institute (CSIR-CEERI), Pilani, Rajasthan, India since the year of 2005. Presently he is working as a Senior Scientist with Integrated Systems Group, CSIR-CEERI, Pilani, in the area of high-performance architecture for real-time image/video processing for ASIC and with FPGA-based platforms. His research interest includes: High-performance computer architecture, VLSI design, System-on-chip (SoCs) and embedded system applications. Dr. Pandey is a Senior Member of IEEE and Life member of Semiconductor Society of India.

Employment

  • Central Electronics Engineering Research Institute CSIR Senior Principal Scientist
    2005 - Present

Education

  • Birla Institute of Technology and Science Ph.D
    2008 - 2015

Projects & Funding

Projects & funding information is unavailable.

Publications

Publications are unavailable.