Yogesh Shrivastava

Employment

Employment history is unavailable.

Education

Education history is unavailable.

Projects & Funding

Projects & funding information is unavailable.

Publications (8)

• Efficient Noise Immune Robust Ternary Subtractor Designs*
  2023 DOI: 10.1007/978-981-19-6661-3_36
  +Save
• Designing of Low-Power High-Speed Noise Immune CNTFET 1-Trit Unbalanced Ternary Subtractor
  Journal of Circuits, Systems and Computers 2022 DOI: 10.1142/S0218126622500827
  +Save
• Design of Compact Reliable Energy Efficient Read Disturb Free 17T CNFET Ternary S-RAM Cell
  IEEE Transactions on Device and Materials Reliability 2021 DOI: 10.1109/TDMR.2021.3111958
  +Save
• Design of High-Speed Low Variation Static Noise Margin Ternary S-RAM Cells
  IEEE Transactions on Device and Materials Reliability 2021 DOI: 10.1109/TDMR.2021.3058159
  +Save
• Design of Efficient Ternary Subtractor
  2021 DOI: 10.1007/978-981-15-6840-4_14
  +Save
• Design of low‐power high‐speed CNFET 1‐trit unbalanced ternary multiplier
  International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 2020 DOI: 10.1002/jnm.2685
  +Save
• Methods to design ternary gates and adders
  VLSI and Post CMOS electronics volume 2 2019
  +Save
• Methods to design ternary gates and adders
  VLSI and Post-CMOS Electronics 2019 DOI: 10.1049/PBCS073G_ch14
  +Save