K.Sarath Chandra

Employment

• VNRVJIET ASSISTANT PROFESSOR
  2013 - Present
• MRECW ASSISTANT PROFESSOR
  2012 - 2013
• AVRSVRCET ASSITANT PROFESSOR
  2009 - 2010

Education

Education history is unavailable.

Projects & Funding

Projects & funding information is unavailable.

Publications (8)

• Design and Analysis of Low Power FinFET SRAM with Leakage Current Reduction Techniques
  Wireless Personal Communications 2023 DOI: 10.1007/s11277-023-10475-4
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• Implementation of N-bit Universal BIST for Testing of Memory and Arithmetic Operator Using FPGA
  Proceedings - 2022 International Conference on Recent Trends in Microelectronics, Automation, Computing and Communications Systems, ICMACC 2022 2022 DOI: 10.1109/ICMACC54824.2022.10093512
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• Design Of Low Power Finfet Sram And Analysis Of Different Leakage Current Reduction Techniques
  ARPN Journal of Engineering and Applied Sciences 2021
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• Electrical characteristics of double gate finfet under different modes of operation
  International Journal of Innovative Technology and Exploring Engineering 2019
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• Research Paper IJRAR- International Journal of Research and Analytical Reviews 717 CMOS REALIZATION OF AN AMPLIFIER-FREE PIPELINE-SAR ADC ARCHITECTURE FOR LOW POWER APPLICATIONS
  International Journal of Research and Analytical Reviews 2018
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• Physical design implementation of high performance CMOS dynamic latch comparator
  Journal of Advanced Research in Dynamical and Control Systems 2018
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• Design and implementation of high performance mil-std-1553b bus controller
  Proceedings - 7th IEEE International Advanced Computing Conference, IACC 2017 2017 DOI: 10.1109/IACC.2017.0065
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• Low Power and High Speed 4-Bit Flash Analog to Digital Converter Using Dynamic Latch Comparator Technique
  International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering 2015 DOI: 10.15662/ijareeie.2015.0408009
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