Rajashekar Shettar

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Publications (26)

• Improvement in computational latency and performance of pipelined interval arithmetic cordic algorithm
  International Journal of Advanced Science and Technology 2020
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• Power-Efficient Reversible Logic Design of S-Box for N-Bit AES
  Advances in Intelligent Systems and Computing 2020 DOI: 10.1007/978-981-15-1084-7_25
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• A novel design and implementation of 8-bit and 16-bit hybrid ALU
  Advances in Intelligent Systems and Computing 2020 DOI: 10.1007/978-3-030-16657-1_4
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• A Face Recognition Based Automatic Attendance Management System by Combining LBP and HOG Features
  Lecture Notes on Data Engineering and Communications Technologies 2019 DOI: 10.1007/978-3-030-03146-6_109
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• A Novel Approach to Optimize Design of n-Bit AES Using Reversible Logic
  Lecture Notes on Data Engineering and Communications Technologies 2019 DOI: 10.1007/978-3-030-03146-6_115
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• A novel design and implementation of 32-bit hybrid ALU
  Lecture Notes in Networks and Systems 2019 DOI: 10.1007/978-981-13-7150-9_25
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• Design and Implementation of Adders and Multiplier in FPGA Using ChipScope: A Performance Improvement
  Lecture Notes in Networks and Systems 2019 DOI: 10.1007/978-981-13-0586-3_2
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• Power-efficient approach to optimize SHA-256 bit using reversible logic
  Lecture Notes in Networks and Systems 2019 DOI: 10.1007/978-981-13-7150-9_29
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• Performance analysis of AES-128 Bits, 192 bits and 256 bits using reversible logic
  9th International Conference on Advances in Computing, Control, and Telecommunication Technologies, ACT 2018 2018
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• Technology enabled active learning for electromagnetic waves and theory
  Proceedings - IEEE 9th International Conference on Technology for Education, T4E 2018 2018 DOI: 10.1109/T4E.2018.00062
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