CV

Chetan Kumar Vudadha

Birla Institute of Technology and Science - Hyderabad Campus, Wipro (India)

ORCID iD 0000-0002-0277-2931

Employment

  • Birla Institute of Technology and Science - Hyderabad Campus Assistant Professor
    2018 - Present
  • Birla Institute of Technology and Science - Hyderabad Campus Visiting Faculty
    2018 - 2018
  • Birla Institute of Technology and Science - Hyderabad Campus Lecturer
    2011 - 2018
  • Wipro (India) Project Engineer
    2006 - 2008

Education

  • Birla Institute of Technology and Science - Hyderabad Campus PhD
    2011 - 2018
  • Birla Institute of Technology and Science - Hyderabad Campus M.E.
    2009 - 2011

Projects & Funding

Projects & funding information is unavailable.

Publications (29)

  • Design of CNFET-based Low-Power Ternary Sequential Logic circuits
    2021 IEEE 21st International Conference on Nanotechnology (NANO) 2021
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  • A novel low power ternary multiplier design using CNFETS
    2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID) 2020
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  • Design of CNTFET-Based Ternary ALU Using 2: 1 Multiplexer Based Approach
    IEEE Transactions on Nanotechnology 2020
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  • FILA: Fault-model for interconnection links in application-specific network-on-chip design
    2020 IEEE International Symposium on Circuits and Systems (ISCAS) 2020
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  • Design of area optimised, energy efficient quaternary circuits using CNTFETs
    2019 IEEE International Symposium on Smart Electronic Systems (iSES)(Formerly iNiS) 2019
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  • Design methodologies for ternary logic circuits
    2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL) 2018
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  • Design of Ternary Logic Circuits Using CNFETs
    Nanoscale Devices 2018
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  • Design of high-speed and power-efficient ternary prefix adders using CNFETS
    IEEE Transactions on nanotechnology 2018
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  • Encoder-based optimization of CNFET-based ternary logic circuits
    IEEE Transactions on Nanotechnology 2018
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  • Energy efficient design of CNFET-based multi-digit ternary adders
    Microelectronics journal 2018
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