CP

Chandrajit Pal

University of Essex, Indian Institute of Technology Hyderabad, University of Calcutta, Maulana Abul Kalam Azad University of Technology, West Bengal, Ceremorphic Technologies Private Limited

ORCID iD 0000-0002-0576-8014
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About

Dr Pal is a Senior Research Officer at the School of Computer Science and Electronic Engineering, University of Essex. In addition, he is a member of the school's Embedded and Intelligent Systems (EIS) Research Group. Before that, he was a National Post-doctoral Fellow (SERB awarded, DST, Govt of India) at IIT Hyderabad, India. He received a PhD in Information Technology from the University of Calcutta. He was awarded the prestigious Presidential DST INSPIRE Fellowship by the Govt of India in 2018 to carry out his doctoral studies. He also worked as a Newton Bhabha Fellow in the School of Electronics and Computer Science department at the University of Southampton, UK in 2016.
His research interests mainly include computer vision and signal processing algorithms, custom computing using FPGAs, embedded systems and hardware/software co-design. Besides his interest in intelligent signal processing algorithms, his research also involves developing energy-efficient heterogeneous architectures to execute deep learning techniques on embedded edge devices with limited resources and latency budgets. His research has resulted in over 40 refereed conference and journal papers, patents and book chapters. Before returning to academic research, Dr Pal worked as an AI Research Engineer and Senior Engineer in the semiconductor industry.



IDEAL: Reducing Carbon Footprints of IoT Devices.
(2025 - Present | EPSRC Project)

BRIEF DESCRIPTION:
Presently contributing to an EPSRC project "IDEAL: Reducing Carbon Footprints of IoT Devices through Extension of Active Lifespans" in collaboration with the University of Glasgow and the University of Oxford. The IDEAL project aims to drastically extend the active lifespan of Internet of Things (IoT) devices from years to decades. This initiative seeks to reduce the substantial carbon footprint associated with manufacturing ICT devices by enabling them to be repurposed and degrade gracefully through novel hardware design, software co-design, formal methods, and machine learning.





Contributed to an EPSRC project by DSBD named MORELLO-HAT in collaboration with the University of Glasgow and the University of Oxford. (2023 - 2025 | EPSRC DsBD Project)

BRIEF DESCRIPTION:
The CHERI project has created the infrastructure for hardware capabilities. The Morello project implements these concepts and tools for the Arm architecture. In terms of programming languages, the focus of CHERI and Morello has been primarily on C but considerable work has also been done on C++ and some more preliminary work on Rust. The Morello-HAT project (Morello High-Level API and Tooling) intends to create a common API that can be used by compiler developers as well as programmers of higher-level languages, to allow them to leverage Morello's HW capabilities to improve memory security and type safety, spatial as well as temporal, of their language and programs.

Employment

  • University of Essex Senior Research Officer
    2025 - 2028
  • University of Essex Senior Research Officer
    2023 - 2025
  • Indian Institute of Technology Hyderabad Senior Research Associate and Project Scientist II
    2022 - 2023
  • Ceremorphic Technologies Private Limited Senior Engineer II
    2019 - 2022
  • Indian Institute of Technology Hyderabad National Post Doctoral Fellow, SERB, DST, Govt of India
    2017 - 2019
  • University of Southampton Newton Bhabha PhD Fellow
    2016 - 2016
  • Sikkim Manipal University Assistant Professor 2
    2010 - 2012

Education

  • University of Calcutta Ph.D.
    2012 - 2018
  • University of Calcutta M.Tech
    2008 - 2010
  • Maulana Abul Kalam Azad University of Technology, West Bengal B.Tech
    2004 - 2008

Projects & Funding

Projects & funding information is unavailable.

Publications (42)