Sresta Valasa

Employment

Employment history is unavailable.

Education

• National Institute of Technology Warangal Doctor of Philosophy
  2023 - 2025
• National Institute of Technology Warangal Junior Research Fellow
  2022 - 2022
• JNTUH COLLEGE OF ENGINEERING JAGTIAL BTECH
  2016 - 2019
• GOVT.PLOYTECHNIC FOR WOMEN, WARANGAL POLYTECHNIC
  2013 - 2016

Projects & Funding

Projects & funding information is unavailable.

Publications (41)

• Engineering the spacer for junctionless comb-shaped nanosheet FETs at Sub-5 nm node: Device to circuit realization
  Micro and Nanostructures 2026 DOI: 10.1016/j.micrna.2026.208723
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• Towards the next era of CMOS scaling: A comprehensive review on the emerging landscape of complementary FET technology
  Materials Science in Semiconductor Processing 2026 DOI: 10.1016/j.mssp.2026.110809
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• Design of energy-efficient LIF neuron using CMOS compatible gate-all-around floating nanosheet FET for bio-inspired spiking neural networks
  Neurocomputing 2026 DOI: 10.1016/j.neucom.2025.131814
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• Role of Dielectric-Semiconductor Interface Traps in Multilayer MoS₂ FinFETs: An Investigation From Device to Circuit
  IEEE Transactions on Dielectrics and Electrical Insulation 2026 DOI: 10.1109/TDEI.2025.3570968
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• Ferroelectric/Dielectric Spacer Engineering in Negative Capacitance MoS2 FinFETs: An Insight Into Digital, Analog/RF, and Circuit Applications
  IEEE Transactions on Dielectrics and Electrical Insulation 2026 DOI: 10.1109/TDEI.2026.3694623
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• Experimental Feasibility-Driven Spacer Material Engineering for Improved Performance in Novel E-shaped Nanosheet FET at Sub-5 Nm Technology Node: Device to Circuit Level Insights
  ECS Journal of Solid State Science and Technology 2026 DOI: 10.1149/2162-8777/ae805a
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• A 3 nm IRDS projection based design space variability and experimental feasibility in junctionless forksheet FET: implications for next-generation digital, analog/RF, and circuit applications
  Solid-State Electronics 2025 DOI: 10.1016/j.sse.2025.109231
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• Comprehensive analysis of tree-shaped nanosheet FETs in junctionless, accumulation, and inversion structures at sub-5 nm node for next-generation digital, analog/RF and circuit applications
  Physica Scripta 2025 DOI: 10.1088/1402-4896/ae132f
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• Radiation Hardness on Dielectric/Ferroelectric Stacked Negative Capacitance Multigate Metal–Oxide–Semiconductor FETs at Sub-3-nm Technology Node: Device to CMOS Inverter Layout
  IEEE Transactions on Dielectrics and Electrical Insulation 2025 DOI: 10.1109/TDEI.2025.3582236
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• Design Insights of Multilayer MoS2 Fin-Shaped FETs for Digital and Analog/RF Applications
  ACS Applied Electronic Materials 2025 DOI: 10.1021/acsaelm.5c00204
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