Sneh Saurabh

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Publications (19)

• Modeling Multiple-Input Switching in Timing Analysis Using Machine Learning
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2021 DOI: 10.1109/TCAD.2020.3009624
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• Implementation of Boolean Functions Using Tunnel Field-Effect Transistors
  IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 2020 DOI: 10.1109/JXCDC.2020.3038073
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• Realizing XOR and XNOR functions using tunnel field-effect transistors
  IEEE Journal of the Electron Devices Society 2020 DOI: 10.1109/JEDS.2020.3025266
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• Resistive Random Access Memory: A Review of Device Challenges
  IETE Technical Review (Institution of Electronics and Telecommunication Engineers, India) 2020 DOI: 10.1080/02564602.2019.1629341
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• Suppression of Ambipolar current in Tunnel Field-Effect Transistor using Field-Plate
  2020 24th International Symposium on VLSI Design and Test, VDAT 2020 2020 DOI: 10.1109/VDAT50263.2020.9190409
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• Realizing boolean functions using probabilistic spin logic (PSL)
  Proceedings - 32nd International Conference on VLSI Design, VLSID 2019 - Held concurrently with 18th International Conference on Embedded Systems, ES 2019 2019 DOI: 10.1109/VLSID.2019.00110
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• Timing Closure Problem: Review of Challenges at Advanced Process Nodes and Solutions
  IETE Technical Review (Institution of Electronics and Telecommunication Engineers, India) 2019 DOI: 10.1080/02564602.2018.1531733
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• Improving the scalability of SOI-based tunnel FETs using ground plane in buried oxide
  IEEE Journal of the Electron Devices Society 2019 DOI: 10.1109/JEDS.2019.2907314
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• Implementing Logic Functions Using Independently-Controlled Gate in Double-Gate Tunnel FETs: Investigation and Analysis
  IEEE Access 2019 DOI: 10.1109/ACCESS.2019.2936610
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• Dopingless 1T DRAM: Proposal, Design, and Analysis
  IEEE Access 2019 DOI: 10.1109/ACCESS.2019.2925525
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