Ganapathi Hegde

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Publications (8)

• Conservative approximation-based full-search block matching algorithm architecture for QCIF digital video employing systolic array architecture
  ETRI Journal 2015 DOI: 10.4218/etrij.15.0114.0504
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• High performance VLSI architecture for 2-D DWT using lifting scheme
  2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015 2015 DOI: 10.1109/VLSI-SATA.2015.7050459
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• A parallel 3-D discrete wavelet transform architecture using pipelined lifting scheme approach for video coding
  International Journal of Electronics 2013 DOI: 10.1080/00207217.2012.743092
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• An efficient 3-dimensional discrete wavelet transform architecture for video processing application
  Journal of Electronics 2012 DOI: 10.1007/s11767-012-0907-7
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• An efficient hardware model for RSA encryption system using Vedic mathematics
  Procedia Engineering 2012 DOI: 10.1016/j.proeng.2012.01.842
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• Systolic array based motion estimation architecture of 3D DWT sub band component for video processing
  International Journal of Signal and Imaging Systems Engineering 2012 DOI: 10.1504/IJSISE.2012.049851
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• An efficient distributive arithmetic based 3-dimensional discrete wavelet transform for video processing
  Proceedings of 2011 International Conference on Process Automation, Control and Computing, PACC 2011 2011 DOI: 10.1109/PACC.2011.5978992
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• Implementation of systolic array architecture for full search block matching algorithm on FPGA
  European Journal of Scientific Research 2009
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