Dr. Baldev Swamy

About

I have 5 years of research experience in FPGA and ASIC design and 6 years of industrial experience in embedded system design. I completed my Ph.D. titled, "Development of High-Performance Stream Processing Hardware Architectures for Deblocking Filters in HEVC" in 2021 at NIT Meghalaya, Shillong, India.

Currently, I am working as a Sr. Software Engineer at Onnet Systems Pvt Ltd. I am looking for a challenging career to engage in working on designing high-performance hardware architectures for video computing systems.

Employment

• VIT Bhopal University

Education

• National Institute of Technology Meghalaya PhD
  2016 - Present

Projects & Funding

Projects & funding information is unavailable.

Publications (3)

• Scalable Wavefront Parallel Streaming Deblocking Filter Hardware for HEVC Decoder
  IEEE Transactions on Consumer Electronics 2020 DOI: 10.1109/TCE.2019.2960565
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• Design and Implementation of Efficient Streaming Deblocking and SAO Filter for HEVC Decoder
  IEEE Transactions on Consumer Electronics 2018 DOI: 10.1109/TCE.2018.2812518
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• Design of streaming deblocking filter for HEVC decoder
  IEEE Transactions on Consumer Electronics 2017 DOI: 10.1109/TCE.2017.014949
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