k Ragini

Employment

• G.Narayanamma Institute of technology&science Professor

Education

Education history is unavailable.

Projects & Funding

Projects & funding information is unavailable.

Publications (46)

• Implementation of 64-Bit Inexact Speculative Half Unit Biased Floating-Point Adder
  Intelligent Computing and Communication 2023 0 citations DOI: 10.1007/978-981-99-1588-0_39
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• Analysis of Serial-In Parallel-Out Finite Field Multiplier Using Various Domino Logic Styles
  Intelligent Computing and Communication 2023 1 citation DOI: 10.1007/978-981-99-1588-0_22
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• Design and Implementation of RNB multiplier Using NP Domino logic
  2022 International Conference on Recent Trends in Microelectronics, Automation, Computing and Communications Systems (ICMACC) 2022
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• Implementation Of Unbiased Rounding For 64-Bit Floating Point Adder
  2022 International Conference on Recent Trends in Microelectronics, Automation, Computing and Communications Systems (ICMACC) 2022
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• Design and Implementation of RNB multiplier Using NP Domino logic
  Proceedings - 2022 International Conference on Recent Trends in Microelectronics, Automation, Computing and Communications Systems, ICMACC 2022 2022 2 citations DOI: 10.1109/ICMACC54824.2022.10093545
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• Design of 32x32 Reversible Unsigned Multiplier Using Dadda Tree Algorithm
  ECS Transactions 2022 0 citations DOI: 10.1149/10701.16251ecst
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• Implementation of Unbiased Rounding for 64-Bit Floating Point Adder
  Proceedings - 2022 International Conference on Recent Trends in Microelectronics, Automation, Computing and Communications Systems, ICMACC 2022 2022 2 citations DOI: 10.1109/ICMACC54824.2022.10093518
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• Design of 4x4 Reversible Multiplier using Reversible TSG Gate,”
  International Journal of Engineering Research in Electronics and Communication Engineering (IJERECE) ISSN (Online) 2394-6849, Vol 8, Issue 3, March 2021,A Google scholar Journal. 2021
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• Design of high performance approximate redundant binary multiplier using 4:2 & 5:2 compressors
  AIP Conference Proceedings 2021 0 citations DOI: 10.1063/5.0074136
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• Design and Implementation of Ternary Logic Circuits for VLSI Applications
  International Journal of Innovative Technology and Exploring Engineering (IJITEE) 2020
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