Neha Paras

Employment

• Jawaharlal Nehru University Assistant Professor
  2023 - Present
• National Institute of Technology Delhi Assistant Professor
  2022 - 2023
• Punjab Engineering College Assistant Professor
  2021 - 2021
• Dr. B. R. Ambedkar National Institute of Technology Jalandhar Assistant Professor
  2021 - 2021

Education

• National Institute of Technology Kurukshetra Ph.D
  2017 - 2020
• Kurukshetra University M.Tech.
  2014 - 2016

Projects & Funding

Projects & funding information is unavailable.

Publications (15)

• Design and analysis of novel La:HfO2 gate stacked ferroelectric tunnel FET for non-volatile memory applications
  Memories - Materials, Devices, Circuits and Systems 2024 DOI: 10.1016/j.memori.2024.100101
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• Impact of the Self-Heating Effect on Nanosheet Field Effect Transistor Performance
  ECS Journal of Solid State Science and Technology 2023 DOI: 10.1149/2162-8777/acb96b
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• Designing of Nonvolatile Memories Utilizing Tunnel Field Effect Transistor
  Tunneling Field Effect Transistors 2023 DOI: 10.1201/9781003327035
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• Performance Analysis of Tunnel Field Effect Transistor for Low‐Power Applications
  Intelligent Green Technologies for Sustainable Smart Cities 2022 DOI: 10.1002/9781119816096.ch10
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• Design and Integration of Vertical TFET and Memristor for Better Realization of Logical Functions
  Silicon 2022 DOI: 10.1007/s12633-022-02047-1
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• Room temperature magento-electric coupling in Pb–Zn substituted Co2Y-hexaferrite
  Journal of Materials Science: Materials in Electronics 2022 DOI: 10.1007/s10854-022-08561-7
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• Linearity Analysis of Line Tunneling Based TFET for High-Performance RF Applications
  Lecture Notes in Electrical Engineering 2021 DOI: 10.1007/978-981-15-5341-7_72
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• A novel vertical tunneling based Ge-source TFET with enhanced DC and RF characteristics for prospect low power applications
  Microelectronic Engineering 2019 DOI: 10.1016/j.mee.2019.111103
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• Insights into the DC, RF/Analog and linearity performance of vertical tunneling based TFET for low-power applications
  Microelectronic Engineering 2019 DOI: 10.1016/j.mee.2019.111043
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• Temperature sensitivity analysis of vertical tunneling based dual metal Gate TFET on analog/RF FOMs
  Applied Physics A 2019 DOI: 10.1007/s00339-019-2621-x
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